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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: wb_dma_ch_rf.v,v 1.3 2001-10-19 04:35:04 rudi Exp $
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// $Id: wb_dma_ch_rf.v,v 1.4 2001-10-30 02:06:17 rudi Exp $
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//
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//
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// $Date: 2001-10-19 04:35:04 $
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// $Date: 2001-10-30 02:06:17 $
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// $Revision: 1.3 $
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// $Revision: 1.4 $
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// $Author: rudi $
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// $Author: rudi $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2001/10/19 04:35:04 rudi
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//
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// - Made the core parameterized
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//
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// Revision 1.2 2001/08/15 05:40:30 rudi
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// Revision 1.2 2001/08/15 05:40:30 rudi
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//
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//
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// - Changed IO names to be more clear.
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// - Changed IO names to be more clear.
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// - Uniquifyed define names to be core specific.
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// - Uniquifyed define names to be core specific.
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// - Added Section 3.10, describing DMA restart.
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// - Added Section 3.10, describing DMA restart.
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// Aliases
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// Aliases
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//
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//
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assign ch_adr0 = CH_EN ? {ch_adr0_r, 2'h0} : 32'h0;
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assign ch_adr0 = CH_EN ? {ch_adr0_r, 2'h0} : 32'h0;
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assign ch_adr1 = CH_EN ? {ch_adr1_r, 2'h0} : 32'h0;
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assign ch_adr1 = CH_EN ? {ch_adr1_r, 2'h0} : 32'h0;
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assign ch_am0 = CH_EN ? {ch_am0_r, 4'h0} : 32'h0;
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assign ch_am0 = (CH_EN & HAVE_CBUF) ? {ch_am0_r, 4'h0} : 32'hffff_fff0;
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assign ch_am1 = CH_EN ? {ch_am1_r, 4'h0} : 32'h0;
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assign ch_am1 = (CH_EN & HAVE_CBUF) ? {ch_am1_r, 4'h0} : 32'hffff_fff0;
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assign sw_pointer = CH_EN ? {sw_pointer_r,2'h0} : 32'h0;
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assign sw_pointer = (CH_EN & HAVE_CBUF) ? {sw_pointer_r,2'h0} : 32'h0;
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assign pointer = CH_EN ? {pointer_r, 3'h0, ptr_valid} : 32'h0;
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assign pointer = CH_EN ? {pointer_r, 3'h0, ptr_valid} : 32'h0;
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assign pointer_s = CH_EN ? {pointer_sr, 4'h0} : 32'h0;
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assign pointer_s = CH_EN ? {pointer_sr, 4'h0} : 32'h0;
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assign ch_csr = CH_EN ? {9'h0, int_src_r, ch_csr_r3, rest_en, ch_csr_r2,
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assign ch_csr = CH_EN ? {9'h0, int_src_r, ch_csr_r3, rest_en, ch_csr_r2,
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ch_err, ch_done, ch_busy, 1'b0, ch_csr_r[8:1], ch_enable} : 32'h0;
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ch_err, ch_done, ch_busy, 1'b0, ch_csr_r[8:1], ch_enable} : 32'h0;
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else
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else
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if(ch_csr_re) int_src_r[0] <= #1 1'b0;
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if(ch_csr_re) int_src_r[0] <= #1 1'b0;
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end
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end
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// Interrupt Output
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// Interrupt Output
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assign int = |(int_src_r & ch_csr_r3);
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assign int = |(int_src_r & ch_csr_r3) & CH_EN;
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// ---------------------------------------------------
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// ---------------------------------------------------
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// TXZS
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// TXZS
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always @(posedge clk)
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always @(posedge clk)
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if(CH_EN)
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if(CH_EN)
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// ---------------------------------------------------
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// ---------------------------------------------------
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// AM0
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// AM0
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always @(posedge clk or negedge rst)
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always @(posedge clk or negedge rst)
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if(!rst) ch_am0_r <= #1 28'hfffffff;
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if(!rst) ch_am0_r <= #1 28'hfffffff;
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else
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else
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if(ch_am0_we & HAVE_CBUF) ch_am0_r <= #1 wb_rf_din[31:4];
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if(ch_am0_we) ch_am0_r <= #1 wb_rf_din[31:4];
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// ---------------------------------------------------
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// ---------------------------------------------------
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// ADR1
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// ADR1
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always @(posedge clk)
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always @(posedge clk)
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if(CH_EN)
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if(CH_EN)
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// Software Pointer Match logic
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// Software Pointer Match logic
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assign cmp_adr = ch_csr[2] ? ch_adr1[30:2] : ch_adr0[30:2];
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assign cmp_adr = ch_csr[2] ? ch_adr1[30:2] : ch_adr0[30:2];
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always @(posedge clk)
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always @(posedge clk)
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ch_dis <= #1 (CH_EN & HAVE_CBUF) ? ((sw_pointer[30:2] == cmp_adr) & sw_pointer[31]) : 1'b0;
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ch_dis <= #1 CH_EN & HAVE_CBUF & (sw_pointer[30:2] == cmp_adr) & sw_pointer[31];
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endmodule
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endmodule
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module wb_dma_ch_rf_dummy(clk, rst,
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module wb_dma_ch_rf_dummy(clk, rst,
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