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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: wb_dma_ch_rf.v,v 1.1 2001-07-29 08:57:02 rudi Exp $
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// $Id: wb_dma_ch_rf.v,v 1.2 2001-08-15 05:40:30 rudi Exp $
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//
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//
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// $Date: 2001-07-29 08:57:02 $
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// $Date: 2001-08-15 05:40:30 $
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// $Revision: 1.1 $
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// $Revision: 1.2 $
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// $Author: rudi $
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// $Author: rudi $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2001/07/29 08:57:02 rudi
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//
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//
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// 1) Changed Directory Structure
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// 2) Added restart signal (REST)
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//
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// Revision 1.3 2001/06/14 08:50:01 rudi
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// Revision 1.3 2001/06/14 08:50:01 rudi
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//
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//
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// Changed Module Name to match file name.
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// Changed Module Name to match file name.
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//
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//
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// Revision 1.2 2001/06/13 02:26:48 rudi
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// Revision 1.2 2001/06/13 02:26:48 rudi
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| Line 197... |
Line 203... |
assign pointer_s = {pointer_sr, 4'h0};
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assign pointer_s = {pointer_sr, 4'h0};
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assign ch_csr = {9'h0, int_src_r, ch_csr_r3, rest_en, ch_csr_r2,
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assign ch_csr = {9'h0, int_src_r, ch_csr_r3, rest_en, ch_csr_r2,
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ch_err, ch_done, ch_busy, 1'b0, ch_csr_r[8:1], ch_enable};
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ch_err, ch_done, ch_busy, 1'b0, ch_csr_r[8:1], ch_enable};
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assign ch_txsz = {5'h0, ch_chk_sz_r, ch_sz_inf, 3'h0, ch_tot_sz_r};
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assign ch_txsz = {5'h0, ch_chk_sz_r, ch_sz_inf, 3'h0, ch_tot_sz_r};
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assign ch_enable = ch_csr_r[0] & (HAVE_CBUF ? !ch_dis : 1'b1);
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assign ch_enable = ch_csr_r[`WDMA_CH_EN] & (HAVE_CBUF ? !ch_dis : 1'b1);
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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//
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//
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// CH0 control signals
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// CH0 control signals
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//
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//
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| Line 217... |
Line 223... |
assign ch_am1_we = wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h5);
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assign ch_am1_we = wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h5);
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assign pointer_we = wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h6);
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assign pointer_we = wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h6);
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assign sw_pointer_we = wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h7);
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assign sw_pointer_we = wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h7);
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assign ch_done_we = (((ch_sel==CH_NO) & dma_done_all) | ndnr) &
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assign ch_done_we = (((ch_sel==CH_NO) & dma_done_all) | ndnr) &
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(ch_csr[`USE_ED] ? ch_eol : !ch_csr[`ARS]);
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(ch_csr[`WDMA_USE_ED] ? ch_eol : !ch_csr[`WDMA_ARS]);
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assign chunk_done_we = (ch_sel==CH_NO) & dma_done;
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assign chunk_done_we = (ch_sel==CH_NO) & dma_done;
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assign ch_err_we = (ch_sel==CH_NO) & dma_err;
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assign ch_err_we = (ch_sel==CH_NO) & dma_err;
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assign ch_csr_dewe = de_csr_we & (ch_sel==CH_NO);
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assign ch_csr_dewe = de_csr_we & (ch_sel==CH_NO);
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assign ch_txsz_dewe = de_txsz_we & (ch_sel==CH_NO);
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assign ch_txsz_dewe = de_txsz_we & (ch_sel==CH_NO);
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assign ch_adr0_dewe = de_adr0_we & (ch_sel==CH_NO);
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assign ch_adr0_dewe = de_adr0_we & (ch_sel==CH_NO);
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| Line 231... |
Line 237... |
assign this_ptr_set = ptr_set & (ch_sel==CH_NO);
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assign this_ptr_set = ptr_set & (ch_sel==CH_NO);
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always @(posedge clk)
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always @(posedge clk)
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ch_rl <= #1 HAVE_ARS & (
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ch_rl <= #1 HAVE_ARS & (
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(rest_en & dma_rest) |
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(rest_en & dma_rest) |
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((ch_sel==CH_NO) & dma_done_all & ch_csr[`ARS] & !ch_csr[`USE_ED])
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((ch_sel==CH_NO) & dma_done_all & ch_csr[`WDMA_ARS] & !ch_csr[`WDMA_USE_ED])
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);
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);
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// ---------------------------------------------------
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// ---------------------------------------------------
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// Pointers
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// Pointers
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| Line 254... |
Line 260... |
always @(posedge clk or negedge rst)
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always @(posedge clk or negedge rst)
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if(!rst) ch_eol <= #1 1'b0;
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if(!rst) ch_eol <= #1 1'b0;
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else
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else
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if(HAVE_ED)
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if(HAVE_ED)
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begin
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begin
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if(ch_csr_dewe) ch_eol <= #1 de_csr[`ED_EOL];
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if(ch_csr_dewe) ch_eol <= #1 de_csr[`WDMA_ED_EOL];
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else
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else
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if(ch_done_we) ch_eol <= #1 1'b0;
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if(ch_done_we) ch_eol <= #1 1'b0;
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end
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end
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else ch_eol <= #1 1'b0;
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else ch_eol <= #1 1'b0;
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| Line 285... |
Line 291... |
if(!rst) ch_csr_r <= #1 1'b0;
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if(!rst) ch_csr_r <= #1 1'b0;
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else
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else
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if(ch_csr_we) ch_csr_r <= #1 wb_rf_din[8:0];
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if(ch_csr_we) ch_csr_r <= #1 wb_rf_din[8:0];
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else
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else
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begin
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begin
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if(ch_done_we) ch_csr_r[`CH_EN] <= #1 1'b0;
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if(ch_done_we) ch_csr_r[`WDMA_CH_EN] <= #1 1'b0;
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if(ch_csr_dewe) ch_csr_r[4:1] <= #1 de_csr[19:16];
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if(ch_csr_dewe) ch_csr_r[4:1] <= #1 de_csr[19:16];
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end
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end
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// done bit
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// done bit
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always @(posedge clk or negedge rst)
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always @(posedge clk or negedge rst)
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if(!rst) ch_done <= #1 1'b0;
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if(!rst) ch_done <= #1 1'b0;
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else
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else
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if(ch_csr_we) ch_done <= #1 !wb_rf_din[`CH_EN];
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if(ch_csr_we) ch_done <= #1 !wb_rf_din[`WDMA_CH_EN];
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else
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else
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if(ch_done_we) ch_done <= #1 1'b1;
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if(ch_done_we) ch_done <= #1 1'b1;
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// busy bit
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// busy bit
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always @(posedge clk)
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always @(posedge clk)
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ch_busy <= #1 (ch_sel==CH_NO) & dma_busy;
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ch_busy <= #1 (ch_sel==CH_NO) & dma_busy;
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// stop bit
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// stop bit
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always @(posedge clk)
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always @(posedge clk)
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ch_stop <= #1 ch_csr_we & wb_rf_din[`STOP];
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ch_stop <= #1 ch_csr_we & wb_rf_din[`WDMA_STOP];
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// error bit
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// error bit
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always @(posedge clk or negedge rst)
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always @(posedge clk or negedge rst)
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if(!rst) ch_err <= #1 1'b0;
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if(!rst) ch_err <= #1 1'b0;
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else
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else
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| Line 369... |
Line 375... |
else
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else
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if(ch_rl)
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if(ch_rl)
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{ch_chk_sz_r, ch_tot_sz_r} <= #1 ch_txsz_s;
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{ch_chk_sz_r, ch_tot_sz_r} <= #1 ch_txsz_s;
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// txsz shadow register
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// txsz shadow register
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/*
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always @(posedge clk)
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if((ch_txsz_we | (rest_en & ch_txsz_dewe & de_fetch_descr) )
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& HAVE_ARS) ch_txsz_s <= #1 {wb_rf_din[26:16], wb_rf_din[11:0]};
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*/
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always @(posedge clk)
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always @(posedge clk)
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if(HAVE_ARS)
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if(HAVE_ARS)
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begin
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begin
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if(ch_txsz_we) ch_txsz_s <= #1 {wb_rf_din[26:16], wb_rf_din[11:0]};
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if(ch_txsz_we) ch_txsz_s <= #1 {wb_rf_din[26:16], wb_rf_din[11:0]};
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else
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else
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if(rest_en & ch_txsz_dewe & de_fetch_descr)
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if(rest_en & ch_txsz_dewe & de_fetch_descr)
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ch_txsz_s[11:0] <= #1 de_txsz[11:0];
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ch_txsz_s[11:0] <= #1 de_txsz[11:0];
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end
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end
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// Infinite Size indicator
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// Infinite Size indicator
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always @(posedge clk)
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always @(posedge clk)
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if(ch_txsz_we) ch_sz_inf <= #1 wb_rf_din[15];
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if(ch_txsz_we) ch_sz_inf <= #1 wb_rf_din[15];
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// ---------------------------------------------------
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// ---------------------------------------------------
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| Line 402... |
Line 399... |
if(ch_adr0_dewe) ch_adr0_r <= #1 de_adr0[31:2];
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if(ch_adr0_dewe) ch_adr0_r <= #1 de_adr0[31:2];
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else
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else
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if(ch_rl) ch_adr0_r <= #1 ch_adr0_s;
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if(ch_rl) ch_adr0_r <= #1 ch_adr0_s;
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// Adr0 shadow register
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// Adr0 shadow register
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/*
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always @(posedge clk)
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if((ch_adr0_we | (rest_en & ch_adr0_dewe & de_fetch_descr) )
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& HAVE_ARS) ch_adr0_s <= #1 wb_rf_din[31:2];
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*/
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always @(posedge clk)
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always @(posedge clk)
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if(HAVE_ARS)
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if(HAVE_ARS)
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begin
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begin
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if(ch_adr0_we) ch_adr0_s <= #1 wb_rf_din[31:2];
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if(ch_adr0_we) ch_adr0_s <= #1 wb_rf_din[31:2];
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else
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else
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if(rest_en & ch_adr0_dewe & de_fetch_descr)
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if(rest_en & ch_adr0_dewe & de_fetch_descr)
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ch_adr0_s <= #1 de_adr0[31:2];
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ch_adr0_s <= #1 de_adr0[31:2];
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end
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end
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// ---------------------------------------------------
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// ---------------------------------------------------
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// AM0
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// AM0
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always @(posedge clk or negedge rst)
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always @(posedge clk or negedge rst)
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if(!rst) ch_am0_r <= #1 28'hfffffff;
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if(!rst) ch_am0_r <= #1 28'hfffffff;
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else
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else
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| Line 435... |
Line 425... |
if(ch_adr1_dewe) ch_adr1_r <= #1 de_adr1[31:2];
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if(ch_adr1_dewe) ch_adr1_r <= #1 de_adr1[31:2];
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else
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else
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if(ch_rl) ch_adr1_r <= #1 ch_adr1_s;
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if(ch_rl) ch_adr1_r <= #1 ch_adr1_s;
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// Adr1 shadow register
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// Adr1 shadow register
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/*
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always @(posedge clk)
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if((ch_adr1_we | (rest_en & ch_adr1_dewe & de_fetch_descr) )
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& HAVE_ARS) ch_adr1_s <= #1 wb_rf_din[31:2];
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*/
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always @(posedge clk)
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always @(posedge clk)
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if(HAVE_ARS)
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if(HAVE_ARS)
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begin
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begin
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if(ch_adr1_we) ch_adr1_s <= #1 wb_rf_din[31:2];
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if(ch_adr1_we) ch_adr1_s <= #1 wb_rf_din[31:2];
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else
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else
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