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Rev 5	Rev 10
Line 35...	Line 35...
`//// ////`	`//// ////`
`/////////////////////////////////////////////////////////////////////`	`/////////////////////////////////////////////////////////////////////`

`// CVS Log`	`// CVS Log`
`//`	`//`
`// $Id: wb_dma_wb_if.v,v 1.1 2001-07-29 08:57:02 rudi Exp $`	`// $Id: wb_dma_wb_if.v,v 1.2 2001-10-19 04:35:04 rudi Exp $`
`//`	`//`
`// $Date: 2001-07-29 08:57:02 $`	`// $Date: 2001-10-19 04:35:04 $`
`// $Revision: 1.1 $`	`// $Revision: 1.2 $`
`// $Author: rudi $`	`// $Author: rudi $`
`// $Locker: $`	`// $Locker: $`
`// $State: Exp $`	`// $State: Exp $`
`//`	`//`
`// Change History:`	`// Change History:`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.1 2001/07/29 08:57:02 rudi`
	`//`
	`//`
	`// 1) Changed Directory Structure`
	`// 2) Added restart signal (REST)`
	`//`
`// Revision 1.2 2001/06/05 10:22:37 rudi`	`// Revision 1.2 2001/06/05 10:22:37 rudi`
`//`	`//`
`//`	`//`
`// - Added Support of up to 31 channels`	`// - Added Support of up to 31 channels`
`// - Added support for 2,4 and 8 priority levels`	`// - Added support for 2,4 and 8 priority levels`
Line 80...	Line 86...
`slv_adr, slv_din, slv_dout, slv_re, slv_we,`	`slv_adr, slv_din, slv_dout, slv_re, slv_we,`
`pt_sel_o, slv_pt_out, slv_pt_in`	`pt_sel_o, slv_pt_out, slv_pt_in`

`);`	`);`

	`parameter rf_addr = 0;`

`input clk, rst;`	`input clk, rst;`

`// --------------------------------------`	`// --------------------------------------`
`// WISHBONE INTERFACE`	`// WISHBONE INTERFACE`

Line 177...	Line 185...
`.mast_pt_in( mast_pt_in ),`	`.mast_pt_in( mast_pt_in ),`
`.mast_pt_out( mast_pt_out )`	`.mast_pt_out( mast_pt_out )`
`);`	`);`


`wb_dma_wb_slv u1(`	`wb_dma_wb_slv #(rf_addr) u1(`
`.clk( clk ),`	`.clk( clk ),`
`.rst( rst ),`	`.rst( rst ),`
`.wb_data_i( wbm_data_i ),`	`.wb_data_i( wbm_data_i ),`
`.wb_data_o( wbm_data_o ),`	`.wb_data_o( wbm_data_o ),`
`.wb_addr_i( wb_addr_i ),`	`.wb_addr_i( wb_addr_i ),`

Line 35...

////                                                             ////

////                                                             ////

/////////////////////////////////////////////////////////////////////

/////////////////////////////////////////////////////////////////////

//  CVS Log

//  CVS Log

//

//

//  $Id: wb_dma_wb_if.v,v 1.1 2001-07-29 08:57:02 rudi Exp $

//  $Id: wb_dma_wb_if.v,v 1.2 2001-10-19 04:35:04 rudi Exp $

//

//

//  $Date: 2001-07-29 08:57:02 $

//  $Date: 2001-10-19 04:35:04 $

//  $Revision: 1.1 $

//  $Revision: 1.2 $

//  $Author: rudi $

//  $Author: rudi $

//  $Locker:  $

//  $Locker:  $

//  $State: Exp $

//  $State: Exp $

//

//

// Change History:

// Change History:

//               $Log: not supported by cvs2svn $

//               $Log: not supported by cvs2svn $

//               Revision 1.1  2001/07/29 08:57:02  rudi

//

//

//               1) Changed Directory Structure

//               2) Added restart signal (REST)

//

//               Revision 1.2  2001/06/05 10:22:37  rudi

//               Revision 1.2  2001/06/05 10:22:37  rudi

//

//

//

//

//               - Added Support of up to 31 channels

//               - Added Support of up to 31 channels

//               - Added support for 2,4 and 8 priority levels

//               - Added support for 2,4 and 8 priority levels

Line 80...

Line 86...

        slv_adr, slv_din, slv_dout, slv_re, slv_we,

        slv_adr, slv_din, slv_dout, slv_re, slv_we,

        pt_sel_o, slv_pt_out, slv_pt_in

        pt_sel_o, slv_pt_out, slv_pt_in

);

);

parameter       rf_addr = 0;

input           clk, rst;

input           clk, rst;

// --------------------------------------

// --------------------------------------

// WISHBONE INTERFACE

// WISHBONE INTERFACE

Line 177...

Line 185...

                .mast_pt_in(    mast_pt_in      ),

                .mast_pt_in(    mast_pt_in      ),

                .mast_pt_out(   mast_pt_out     )

                .mast_pt_out(   mast_pt_out     )

);

);

wb_dma_wb_slv   u1(

wb_dma_wb_slv #(rf_addr)        u1(

                .clk(           clk             ),

                .clk(           clk             ),

                .rst(           rst             ),

                .rst(           rst             ),

                .wb_data_i(     wbm_data_i      ),

                .wb_data_i(     wbm_data_i      ),

                .wb_data_o(     wbm_data_o      ),

                .wb_data_o(     wbm_data_o      ),

                .wb_addr_i(     wb_addr_i       ),

                .wb_addr_i(     wb_addr_i       ),

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[/] [wb_dma/] [trunk/] [rtl/] [verilog/] [wb_dma_wb_if.v] - Diff between revs 5 and 10