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[/] [wb_dma/] [trunk/] [rtl/] [verilog/] [wb_dma_wb_slv.v] - Diff between revs 8 and 10
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: wb_dma_wb_slv.v,v 1.2 2001-08-15 05:40:30 rudi Exp $
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// $Id: wb_dma_wb_slv.v,v 1.3 2001-10-19 04:35:04 rudi Exp $
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//
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//
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// $Date: 2001-08-15 05:40:30 $
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// $Date: 2001-10-19 04:35:04 $
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// $Revision: 1.2 $
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// $Revision: 1.3 $
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// $Author: rudi $
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// $Author: rudi $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2001/08/15 05:40:30 rudi
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//
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// - Changed IO names to be more clear.
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// - Uniquifyed define names to be core specific.
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// - Added Section 3.10, describing DMA restart.
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//
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// Revision 1.1 2001/07/29 08:57:02 rudi
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// Revision 1.1 2001/07/29 08:57:02 rudi
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//
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//
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//
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//
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// 1) Changed Directory Structure
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// 1) Changed Directory Structure
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// 2) Added restart signal (REST)
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// 2) Added restart signal (REST)
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// Pass through Interface
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// Pass through Interface
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pt_sel, slv_pt_out, slv_pt_in
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pt_sel, slv_pt_out, slv_pt_in
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);
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);
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parameter rf_addr = 0;
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input clk, rst;
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input clk, rst;
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// --------------------------------------
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// --------------------------------------
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// WISHBONE INTERFACE
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// WISHBONE INTERFACE
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