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architecture rtl of fifo is
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architecture rtl of fifo is
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type t_memory is array(memoryDepth-1 downto 0) of i_transactor.t_msg;
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type t_memory is array(memoryDepth-1 downto 0) of i_transactor.t_msg;
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signal memory:t_memory;
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signal memory:t_memory;
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signal ptr:natural range 0 to memoryDepth-1;
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signal ptr:natural range 0 to memoryDepth-1;
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/* FIFO control signalling. */
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signal fifoCtrl:t_fifo;
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/*
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/*
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writeRequest and readRequest are inputs. This indicate that a block is requesting to write to or
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writeRequest and readRequest are inputs. This indicate that a block is requesting to write to or
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read from the FIFO.
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read from the FIFO.
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For write requests, the external block requests to write some data into the FIFO. The data
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For write requests, the external block requests to write some data into the FIFO. The data
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is attached as part of the write request (writeRequest.message).
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is attached as part of the write request (writeRequest.message).
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/* TODO recheck pipelining. */
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/* TODO recheck pipelining. */
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process(clk) is begin
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process(clk) is begin
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if falling_edge(clk) then
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if falling_edge(clk) then
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i_writeRequest <= fifoInterface.writeRequest;
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i_writeRequest <= fifoInterface.writeRequest;
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i_readRequest <= fifoInterface.readRequest;
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i_readRequest <= fifoInterface.readRequest;
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i_full <= fifoInterface.full;
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i_full <= fifoCtrl.full;
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i_empty <= fifoInterface.empty;
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i_empty <= fifoCtrl.empty;
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end if;
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end if;
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end process;
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end process;
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fifoInterface.pctFilled<=to_unsigned(ptr*100/(memoryDepth-1), fifoInterface.pctFilled'length);
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fifoCtrl.pctFilled<=to_unsigned(ptr*100/(memoryDepth-1), fifoCtrl.pctFilled'length);
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process(clk) is begin
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process(clk) is begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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fifoInterface.nearFull<=true when fifoInterface.pctFilled>=d"75" and fifoInterface.pctFilled<d"100" else false;
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fifoCtrl.nearFull<=true when fifoCtrl.pctFilled>=d"75" and fifoCtrl.pctFilled<d"100" else false;
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fifoInterface.full<=true when fifoInterface.pctFilled=d"100" else false;
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fifoCtrl.full<=true when fifoCtrl.pctFilled=d"100" else false;
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fifoInterface.nearEmpty<=true when fifoInterface.pctFilled<=d"25" and fifoInterface.pctFilled>d"0" else false;
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fifoCtrl.nearEmpty<=true when fifoCtrl.pctFilled<=d"25" and fifoCtrl.pctFilled>d"0" else false;
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fifoInterface.empty<=true when fifoInterface.pctFilled=d"0" else false;
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fifoCtrl.empty<=true when fifoCtrl.pctFilled=d"0" else false;
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end if;
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end if;
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end process;
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end process;
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process(clk) is begin
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process(clk) is begin
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if falling_edge(clk) then
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if falling_edge(clk) then
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fifoInterface.overflow<=fifoInterface.full and write;
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fifoCtrl.overflow<=fifoCtrl.full and write;
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fifoInterface.underflow<=fifoInterface.empty and read;
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fifoCtrl.underflow<=fifoCtrl.empty and read;
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end if;
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end if;
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end process;
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end process;
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end architecture rtl;
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end architecture rtl;
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