| Line 77... |
Line 77... |
when the FIFO is empty.
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when the FIFO is empty.
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*/
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*/
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signal i_writeRequest,i_readRequest:i_transactor.t_bfm;
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signal i_writeRequest,i_readRequest:i_transactor.t_bfm;
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signal i_full,i_empty:boolean;
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signal i_full,i_empty:boolean;
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signal write,read:boolean;
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signal write,read:boolean;
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|
|
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signal writeRequested, readRequested: boolean;
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begin
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begin
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/* Registers and pipelines. */
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/* TODO recheck pipelining. */
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process(clk) is begin
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if falling_edge(clk) then
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/* TODO add buffers for pipelined request signals,
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i.e., add a flip-flop and a buffer.
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*/
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i_writeRequest <= fifoInterface.writeRequest after 1 ps;
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i_readRequest <= fifoInterface.readRequest after 1 ps;
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|
|
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i_full <= fifoCtrl.full;
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i_empty <= fifoCtrl.empty;
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end if;
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end process;
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|
|
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/* Synchronous FIFO. */
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controller: process(reset,clk) is begin
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controller: process(reset,clk) is begin
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if reset then
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--if reset then
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fifoInterface.readResponse.message<=(others=>'Z');
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-- fifoInterface.readResponse.message<=(others=>'Z');
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fifoInterface.readResponse.trigger<=false;
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-- fifoInterface.readResponse.trigger<=false;
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elsif falling_edge(clk) then
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if falling_edge(clk) then
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/* Default assignments. */
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/* Default assignments. */
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fifoInterface.readResponse.trigger<=false;
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fifoInterface.readResponse.trigger<=false;
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fifoInterface.writeResponse.trigger<=false;
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fifoInterface.writeResponse.trigger<=false;
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|
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/* Write request.
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/* Write request.
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Safety control: allow writing only when FIFO is not full.
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Safety control: allow writing only when FIFO is not full.
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*/
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*/
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--if i_pctFilled<d"100" and (fifoInterface.writeRequest.trigger xor i_writeRequest.trigger) then
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--if i_pctFilled<d"100" and (fifoInterface.writeRequest.trigger xor i_writeRequest.trigger) then
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if not i_full and (fifoInterface.writeRequest.trigger xor i_writeRequest.trigger) then
|
--if not i_full and (fifoInterface.writeRequest.trigger xor i_writeRequest.trigger) then -- TODO change to write
|
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if not i_full and write then
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fifoInterface.writeResponse.trigger<=true;
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fifoInterface.writeResponse.trigger<=true;
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memory(ptr)<=fifoInterface.writeRequest.message;
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memory(ptr)<=fifoInterface.writeRequest.message;
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end if;
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end if;
|
|
|
/* Read request.
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/* Read request.
|
Safety control: allow reading only when FIFO is not empty.
|
Safety control: allow reading only when FIFO is not empty.
|
*/
|
*/
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if not i_empty and (fifoInterface.readRequest.trigger xor i_readRequest.trigger) then
|
--if not i_empty and (fifoInterface.readRequest.trigger xor i_readRequest.trigger) then -- TODO change to read
|
|
if not i_empty and read then
|
fifoInterface.readResponse.trigger<=true;
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fifoInterface.readResponse.trigger<=true;
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fifoInterface.readResponse.message<=memory(ptr);
|
fifoInterface.readResponse.message<=memory(ptr);
|
end if;
|
end if;
|
|
|
|
/* Synchronous reset. */
|
|
if reset then
|
|
fifoInterface.readResponse.message<=(others=>'Z');
|
|
fifoInterface.readResponse.trigger<=false;
|
|
end if;
|
end if;
|
end if;
|
end process controller;
|
end process controller;
|
|
|
write<=fifoInterface.writeRequest.trigger xor i_writeRequest.trigger;
|
write<=fifoInterface.writeRequest.trigger xor i_writeRequest.trigger;
|
read<=fifoInterface.readRequest.trigger xor i_readRequest.trigger;
|
read<=fifoInterface.readRequest.trigger xor i_readRequest.trigger;
|
|
|
|
/* Request indicator. Derived from fifoInterface.writeRequest.trigger
|
|
and fifoInterface.readRequest.trigger.
|
|
Asserts when there are incoming requests.
|
|
*/
|
|
process(clk) is begin
|
|
if falling_edge(clk) then
|
|
writeRequested <= fifoInterface.writeRequest.trigger xor i_writeRequest.trigger;
|
|
readRequested <= fifoInterface.readRequest.trigger xor i_readRequest.trigger;
|
|
end if;
|
|
end process;
|
|
|
addrPointer: process(reset,clk) is begin
|
addrPointer: process(reset,clk) is begin
|
if reset then ptr<=0;
|
if reset then ptr<=0;
|
elsif falling_edge(clk) then
|
elsif falling_edge(clk) then
|
/* Increment or decrement the address pointer only when write or read is HIGH;
|
/* Increment or decrement the address pointer only when write or read is HIGH;
|
do nothing when both are HIGH or when both are LOW.
|
do nothing when both are HIGH or when both are LOW.
|
| Line 126... |
Line 163... |
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process addrPointer;
|
end process addrPointer;
|
|
|
/* Registers and pipelines. */
|
|
/* TODO recheck pipelining. */
|
|
process(clk) is begin
|
|
if falling_edge(clk) then
|
|
i_writeRequest <= fifoInterface.writeRequest;
|
|
i_readRequest <= fifoInterface.readRequest;
|
|
i_full <= fifoCtrl.full;
|
|
i_empty <= fifoCtrl.empty;
|
|
end if;
|
|
end process;
|
|
|
|
fifoCtrl.pctFilled<=to_unsigned(ptr*100/(memoryDepth-1), fifoCtrl.pctFilled'length);
|
fifoCtrl.pctFilled<=to_unsigned(ptr*100/(memoryDepth-1), fifoCtrl.pctFilled'length);
|
|
|
process(clk) is begin
|
process(clk) is begin
|
if rising_edge(clk) then
|
if rising_edge(clk) then
|
fifoCtrl.nearFull<=true when fifoCtrl.pctFilled>=d"75" and fifoCtrl.pctFilled<d"100" else false;
|
fifoCtrl.nearFull<=true when fifoCtrl.pctFilled>=d"75" and fifoCtrl.pctFilled<d"100" else false;
|
