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[/] [wb_lpc/] [trunk/] [examples/] [pci_lpc/] [top_pci_lpc_host.v] - Diff between revs 9 and 12

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Line 1... Line 1... 
//////////////////////////////////////////////////////////////////////
 
//////////////////////////////////////////////////////////////////////
 
////                                                              ////
 
////                                                              ////
 
////  $Id: top_pci_lpc_host.v,v 1.2 2008-03-05 16:14:32 hharte Exp $   ////
 
////  $Id: top_pci_lpc_host.v,v 1.3 2008-03-10 14:17:13 hharte Exp $   ////
 
////  top_pci_lpc_host.v - Top Level for PCI to LPC Host          ////
 
////  top_pci_lpc_host.v - Top Level for PCI to LPC Host          ////
 
////  for the Enterpoint Raggedstone1 PCI Card.  Based on the     ////
 
////  for the Enterpoint Raggedstone1 PCI Card.  Based on the     ////
 
////  OpenCores raggedstone project, and uses the OpenCores       ////
 
////  OpenCores raggedstone project, and uses the OpenCores       ////
 
////  pci32tlite core.                                            ////
 
////  pci32tlite core.                                            ////
 
////                                                              ////
 
////                                                              ////
Line 62... Line 62... 
    CBE3,
 
    CBE3,
 
 
 
 
 
    DISP_SEL,
 
    DISP_SEL,
 
    DISP_LED,
 
    DISP_LED,
 
 
 
 
 
 
 
    LPC_RST,
 
    LPC_CLK,
 
    LPC_CLK,
 
    LFRAME,
 
    LFRAME,
 
    LAD,
 
    LAD,
 
    LAD_OE,
 
    LAD_OE,
 
    LPC_INT,
 
    LPC_INT,
 
 
 
 
 
 
 
    LPC_GND,
 
 
 
 
 
    PREVENT_STRIPPING_OF_UNUSED_INPUTS
 
    PREVENT_STRIPPING_OF_UNUSED_INPUTS
 
);
 
);
 
 
 
 
 
input           CLK ;
 
input           CLK ;
 
input           RST ;
 
input           RST ;
Line 97... Line 100... 
input           REQ ;       // attribute s of PCI_nREQ: signal is "yes"; 
input           REQ ;       // attribute s of PCI_nREQ: signal is "yes"; 
input           GNT ;       // attribute s of PCI_nGNT: signal is "yes"; 
input           GNT ;       // attribute s of PCI_nGNT: signal is "yes"; 
output  [3:0]   DISP_SEL ;
 
output  [3:0]   DISP_SEL ;
 
output  [6:0]   DISP_LED ;
 
output  [6:0]   DISP_LED ;
 
 
 
 
 
 
 
output          LPC_RST;
 
output          LPC_CLK;
 
output          LPC_CLK;
 
output          LFRAME;
 
output          LFRAME;
 
inout   [3:0]   LAD;
 
inout   [3:0]   LAD;
 
input           LPC_INT;
 
inout           LPC_INT;
 
output          LAD_OE;
 
output          LAD_OE;
 
 
 
 
 
 
 
output  [6:0]   LPC_GND;
 
 
 
assign LPC_GND = 7'b0000000;
 
 
 
 
 
output          PREVENT_STRIPPING_OF_UNUSED_INPUTS ;
 
output          PREVENT_STRIPPING_OF_UNUSED_INPUTS ;
 
 
 
 
 
assign PREVENT_STRIPPING_OF_UNUSED_INPUTS = REQ & GNT;
 
assign PREVENT_STRIPPING_OF_UNUSED_INPUTS = REQ & GNT;
 
 
 
 
 
wire    [2:0]   dma_chan_i = 3'b000;
 
wire    [2:0]   dma_chan_i = 3'b000;
Line 114... Line 121... 
wire            lframe_o;
 
wire            lframe_o;
 
wire    [3:0]   lad_i;
 
wire    [3:0]   lad_i;
 
wire    [3:0]   lad_o;
 
wire    [3:0]   lad_o;
 
wire            host_lad_oe;
 
wire            host_lad_oe;
 
 
 
 
 
 
 
assign LPC_RST = RST;
 
assign LAD = (host_lad_oe ? lad_o : 4'bzzzz);
 
assign LAD = (host_lad_oe ? lad_o : 4'bzzzz);
 
assign LAD_OE = host_lad_oe;
 
assign LAD_OE = host_lad_oe;
 
assign LPC_CLK = CLK;
 
 
 
assign LFRAME = ~lframe_o;
 
assign LFRAME = ~lframe_o;
 
 
 
 
 
wire    [3:0]   CBE_in =
 
wire    [3:0]   CBE_in =
 
{
 
{
 
    CBE3,
 
    CBE3,
 
    CBE2,
 
    CBE2,
 
    CBE1,
 
    CBE1,
 
    CBE0
 
    CBE0
 
} ;
 
} ;
 
 
 
 
 
wire            PCI_CLK = CLK;
 
 
 
 
 
 
 
wire    [24:0]  wb_adr_o;
 
wire    [24:0]  wb_adr_o;
 
wire    [31:0]  wb_dat_i;
 
wire    [31:0]  wb_dat_i;
 
wire    [31:0]  wb_dat_o;
 
wire    [31:0]  wb_dat_o;
 
wire    [3:0]   wb_sel_o;
 
wire    [3:0]   wb_sel_o;
 
wire    [1:0]   wb_tga;
 
wire    [1:0]   wb_tga;
Line 145... Line 150... 
wire            wb_int_i;
 
wire            wb_int_i;
 
 
 
 
 
//assign wb_tga = wb_adr_o[17:16];  // I/O Cycle
 
//assign wb_tga = wb_adr_o[17:16];  // I/O Cycle
 
assign wb_tga = 2'b10;  // Firmware cycle
 
assign wb_tga = 2'b10;  // Firmware cycle
 
 
 
 
 
assign wb_int_i = ~LPC_INT;
 
 
 
 
 
 
 
// Instantiate the pci32tlite module
 
// Instantiate the pci32tlite module
 
pci32tLite #(
 
pci32tLite #(
 
    .vendorID(16'h10ee),
 
    .vendorID(16'h10ee),
 
    .deviceID(16'hf00d),
 
    .deviceID(16'hf00d),
 
    .revisionID(8'h01),
 
    .revisionID(8'h01),
Line 185... Line 188... 
    .wb_rty_i(wb_rty_i),
 
    .wb_rty_i(wb_rty_i),
 
    .wb_err_i(wb_err_i),
 
    .wb_err_i(wb_err_i),
 
    .wb_int_i(wb_int_i)
 
    .wb_int_i(wb_int_i)
 
    );
 
    );
 
 
 
 
 
 
 
// Instantiate the LPC clock generator.
 
 
 
// The LPC clock is phase shifted by about -3ns to compensate
 
 
 
// for the skew to the LPC slave over the cable.
 
 
 
lpc_clkgen lpc_clkgen (
 
 
 
    .CLKIN_IN(CLK),
 
 
 
    .RST_IN(~RST),
 
 
 
    .CLKIN_IBUFG_OUT(PCI_CLK),
 
 
 
    .CLK0_OUT(LPC_CLK)
 
 
 
    );
 
 
 
 
 
wb_lpc_host lpc_host (
 
wb_lpc_host lpc_host (
 
    .clk_i(CLK),
 
    .clk_i(PCI_CLK),
 
    .nrst_i(RST),
 
    .nrst_i(RST),
 
    .wbs_adr_i(wb_adr_o),
 
    .wbs_adr_i(wb_adr_o),
 
    .wbs_dat_o(wb_dat_i),
 
    .wbs_dat_o(wb_dat_i),
 
    .wbs_dat_i(wb_dat_o),
 
    .wbs_dat_i(wb_dat_o),
 
    .wbs_sel_i(wb_sel_o),
 
    .wbs_sel_i(wb_sel_o),
Line 205... Line 218... 
    .lad_i(LAD),
 
    .lad_i(LAD),
 
    .lad_o(lad_o),
 
    .lad_o(lad_o),
 
    .lad_oe(host_lad_oe)
 
    .lad_oe(host_lad_oe)
 
    );
 
    );
 
 
 
 
 
 
 
wire         serirq_mode = 1'b0;
 
 
 
wire  [31:0] irq_o;
 
 
 
wire         serirq_i;
 
 
 
wire         serirq_o;
 
 
 
wire         serirq_oe;
 
 
 
 
 
 
 
assign LPC_INT = (serirq_oe ? serirq_o : 1'bz);
 
 
 
assign serirq_i = LPC_INT;
 
 
 
assign wb_int_i = ~irq_o[1];
 
 
 
// Instantiate the module
 
 
 
serirq_host lpc_serirq_host (
 
 
 
    .clk_i(PCI_CLK),
 
 
 
    .nrst_i(RST),
 
 
 
    .serirq_mode_i(serirq_mode),
 
 
 
    .irq_o(irq_o),
 
 
 
    .serirq_o(serirq_o),
 
 
 
    .serirq_i(serirq_i),
 
 
 
    .serirq_oe(serirq_oe)
 
 
 
    );
 
 
 
 
 
// The 7-segment display is write-only from the PCI interface.
 
// The 7-segment display is write-only from the PCI interface.
 
// Use some dummy nets for inputs that are ignored.
 
// Use some dummy nets for inputs that are ignored.
 
wire    [31:0]  wb2_dat_i;
 
wire    [31:0]  wb2_dat_i;
 
wire            wb2_ack_i;
 
wire            wb2_ack_i;
 
wire            wb2_err_i;
 
wire            wb2_err_i;
 
wire            wb2_int_i;
 
wire            wb2_int_i;
 
 
 
 
 
// Instantiate the 7-Segment module on the host
 
// Instantiate the 7-Segment module on the host
 
wb_7seg seven_seg0 (
 
wb_7seg seven_seg0 (
 
    .clk_i(CLK),
 
    .clk_i(PCI_CLK),
 
    .nrst_i(RST),
 
    .nrst_i(RST),
 
    .wb_adr_i(wb_adr_o),
 
    .wb_adr_i(wb_adr_o),
 
    .wb_dat_o(wb2_dat_i),
 
    .wb_dat_o(wb2_dat_i),
 
    .wb_dat_i(wb_dat_o),
 
    .wb_dat_i(wb_dat_o),
 
    .wb_sel_i(wb_sel_o),
 
    .wb_sel_i(wb_sel_o),
Line 229... Line 262... 
    .wb_err_o(wb2_err_i),
 
    .wb_err_o(wb2_err_i),
 
    .wb_int_o(wb2_int_i),
 
    .wb_int_o(wb2_int_i),
 
    .DISP_SEL(DISP_SEL),
 
    .DISP_SEL(DISP_SEL),
 
    .DISP_LED(DISP_LED)
 
    .DISP_LED(DISP_LED)
 
    );
 
    );
 
 
 
endmodule
 
 
 
 
 
 
 
 
 
 
 
// FPGA-specific: use a Xilinx DCM Block to deskew the LPC_CLK
 
 
 
module lpc_clkgen(CLKIN_IN,
 
 
 
                  RST_IN,
 
 
 
                  CLKIN_IBUFG_OUT,
 
 
 
                  CLK0_OUT);
 
 
 
 
 
 
 
    input CLKIN_IN;
 
 
 
    input RST_IN;
 
 
 
    output CLKIN_IBUFG_OUT;
 
 
 
    output CLK0_OUT;
 
 
 
 
 
 
 
    wire CLKFB_IN;
 
 
 
    wire CLKIN_IBUFG;
 
 
 
    wire CLK0_BUF;
 
 
 
    wire GND_BIT;
 
 
 
 
 
 
 
    assign GND_BIT = 0;
 
 
 
    assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
 
 
 
    assign CLK0_OUT = CLKFB_IN;
 
 
 
    IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN),
 
 
 
                            .O(CLKIN_IBUFG));
 
 
 
    BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
 
 
 
                         .O(CLKFB_IN));
 
 
 
    DCM DCM_INST (.CLKFB(CLKFB_IN),
 
 
 
                  .CLKIN(CLKIN_IBUFG),
 
 
 
                  .DSSEN(GND_BIT),
 
 
 
                  .PSCLK(GND_BIT),
 
 
 
                  .PSEN(GND_BIT),
 
 
 
                  .PSINCDEC(GND_BIT),
 
 
 
                  .RST(RST_IN),
 
 
 
                  .CLKDV(),
 
 
 
                  .CLKFX(),
 
 
 
                  .CLKFX180(),
 
 
 
                  .CLK0(CLK0_BUF),
 
 
 
                  .CLK2X(),
 
 
 
                  .CLK2X180(),
 
 
 
                  .CLK90(),
 
 
 
                  .CLK180(),
 
 
 
                  .CLK270(),
 
 
 
                  .LOCKED(),
 
 
 
                  .PSDONE(),
 
 
 
                  .STATUS());
 
 
 
    defparam DCM_INST.CLK_FEEDBACK = "1X";
 
 
 
    defparam DCM_INST.CLKDV_DIVIDE = 2.0;
 
 
 
    defparam DCM_INST.CLKFX_DIVIDE = 1;
 
 
 
    defparam DCM_INST.CLKFX_MULTIPLY = 4;
 
 
 
    defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
 
 
 
    defparam DCM_INST.CLKIN_PERIOD = 30.000;
 
 
 
    defparam DCM_INST.CLKOUT_PHASE_SHIFT = "FIXED";
 
 
 
    defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
 
 
 
    defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW";
 
 
 
    defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW";
 
 
 
    defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE";
 
 
 
    defparam DCM_INST.FACTORY_JF = 16'h8080;
 
 
 
    defparam DCM_INST.PHASE_SHIFT = -18;
 
 
 
    defparam DCM_INST.STARTUP_WAIT = "FALSE";
 
endmodule
 
endmodule
 
 
 
// End of FPGA-specific
 
 
 
 
 
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