URL https://opencores.org/ocsvn/wb_lpc/wb_lpc/trunk

Subversion Repositories wb_lpc

[/] [wb_lpc/] [trunk/] [examples/] [pci_lpc/] [top_pci_lpc_host.v] - Diff between revs 7 and 9

Rev 7	Rev 9
Line 1...	Line 1...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//// ////`	`//// ////`
`//// $Id: top_pci_lpc_host.v,v 1.1 2008-03-05 05:58:41 hharte Exp $ ////`	`//// $Id: top_pci_lpc_host.v,v 1.2 2008-03-05 16:14:32 hharte Exp $ ////`
`//// top_pci_lpc_host.v - Top Level for PCI to LPC Host ////`	`//// top_pci_lpc_host.v - Top Level for PCI to LPC Host ////`
`//// for the Enterpoint Raggedstone1 PCI Card. Based on the ////`	`//// for the Enterpoint Raggedstone1 PCI Card. Based on the ////`
`//// OpenCores raggedstone project, and uses the OpenCores ////`	`//// OpenCores raggedstone project, and uses the OpenCores ////`
`//// pci32tlite core. ////`	`//// pci32tlite core. ////`
`//// ////`	`//// ////`
Line 149...	Line 149...

`assign wb_int_i = ~LPC_INT;`	`assign wb_int_i = ~LPC_INT;`

`// Instantiate the pci32tlite module`	`// Instantiate the pci32tlite module`
`pci32tLite #(`	`pci32tLite #(`
`// .vendorID(16'h10ee),`	`.vendorID(16'h10ee),`
`// .deviceID(16'hf00d),`	`.deviceID(16'hf00d),`
`// .revisionID(8'h01),`	`.revisionID(8'h01),`
`.vendorID(16'h14e4),`
`.deviceID(16'h43f5),`
`.revisionID(8'h0a),`
`.subsystemID(16'h0),`	`.subsystemID(16'h0),`
`.subsystemvID(16'h0),`	`.subsystemvID(16'h0),`
`.BARS("1BARMEM"),`	`.BARS("1BARMEM"),`
`.WBSIZE(32),`	`.WBSIZE(32),`
`.WBENDIAN("LITTLE"))`	`.WBENDIAN("LITTLE"))`