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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// $Id: serirq_host.v,v 1.1 2008-03-10 14:08:13 hharte Exp $ ////
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//// $Id: serirq_host.v,v 1.2 2008-12-27 19:46:18 hharte Exp $ ////
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//// serirq_host.v - SERIRQ Host Controller ////
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//// serirq_host.v - SERIRQ Host Controller ////
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//// ////
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//// ////
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//// This file is part of the Wishbone LPC Bridge project ////
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//// This file is part of the Wishbone LPC Bridge project ////
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//// http://www.opencores.org/projects/wb_lpc/ ////
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//// http://www.opencores.org/projects/wb_lpc/ ////
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//// ////
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//// ////
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serirq_o, serirq_i, serirq_oe
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serirq_o, serirq_i, serirq_oe
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);
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);
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// Wishbone Slave Interface
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// Wishbone Slave Interface
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input clk_i;
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input clk_i;
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input nrst_i; // Active low reset.
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input nrst_i; // Active low reset.
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input serirq_mode_i;
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input serirq_mode_i; // Mode selection, 0=Continuous, 1=Quiet
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// SERIRQ Master Interface
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// SERIRQ Master Interface
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output reg serirq_o; // SERIRQ output
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output reg serirq_o; // SERIRQ output
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input serirq_i; // SERIRQ Input
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input serirq_i; // SERIRQ Input
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output reg serirq_oe; // SERIRQ Output Enable
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output reg serirq_oe; // SERIRQ Output Enable
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begin
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begin
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start_cnt <= 3'b000;
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start_cnt <= 3'b000;
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state <= `SERIRQ_ST_START;
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state <= `SERIRQ_ST_START;
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end
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end
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else if((current_mode == `SERIRQ_MODE_QUIET) && (serirq_mode_i == `SERIRQ_MODE_CONTINUOUS))
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else if((current_mode == `SERIRQ_MODE_QUIET) && (serirq_mode_i == `SERIRQ_MODE_CONTINUOUS))
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begin // Switch to Continuous mode if by starting a new cycle to inform the slaves.
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begin // Switch to Continuous mode by starting a new cycle to inform the slaves.
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start_cnt <= 3'b000;
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start_cnt <= 3'b000;
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state <= `SERIRQ_ST_START;
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state <= `SERIRQ_ST_START;
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end
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end
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else
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else
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state <= `SERIRQ_ST_IDLE;
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state <= `SERIRQ_ST_IDLE;
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`SERIRQ_ST_STOP:
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`SERIRQ_ST_STOP:
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begin
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begin
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serirq_o <= 1'b0;
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serirq_o <= 1'b0;
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serirq_oe <= 1'b1;
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serirq_oe <= 1'b1;
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stop_cnt <= stop_cnt + 1;
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stop_cnt <= stop_cnt + 1;
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if(stop_cnt == (serirq_mode_i ? 2'b10 : 2'b01)) begin
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if(stop_cnt == (serirq_mode_i ? 2'b01 : 2'b10)) begin
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state <= `SERIRQ_ST_STOP_R;
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state <= `SERIRQ_ST_STOP_R;
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end
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end
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else begin
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else begin
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state <= `SERIRQ_ST_STOP;
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state <= `SERIRQ_ST_STOP;
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end
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end
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