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[/] [wb_lpc/] [trunk/] [rtl/] [verilog/] [serirq_slave.v] - Diff between revs 11 and 19
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Rev 19 |
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Line 1... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// $Id: serirq_slave.v,v 1.1 2008-03-10 14:08:13 hharte Exp $ ////
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//// $Id: serirq_slave.v,v 1.2 2008-12-27 19:46:18 hharte Exp $ ////
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//// serirq_slave.v - Wishbone Slave to SERIRQ Host Bridge ////
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//// serirq_slave.v - Wishbone Slave to SERIRQ Host Bridge ////
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//// ////
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//// ////
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//// This file is part of the Wishbone LPC Bridge project ////
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//// This file is part of the Wishbone LPC Bridge project ////
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//// http://www.opencores.org/projects/lpc/ ////
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//// http://www.opencores.org/projects/lpc/ ////
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//// ////
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//// ////
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Line 162... |
Line 162... |
case (stop_clk_cnt)
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case (stop_clk_cnt)
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4'h2:
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4'h2:
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begin
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begin
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found_stop <= 1'b1;
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found_stop <= 1'b1;
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found_start <= 1'b0;
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found_start <= 1'b0;
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serirq_mode <= `SERIRQ_MODE_CONTINUOUS;
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serirq_mode <= `SERIRQ_MODE_QUIET;
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end
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end
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4'h3:
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4'h3:
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begin
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begin
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found_stop <= 1'b1;
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found_stop <= 1'b1;
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found_start <= 1'b0;
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found_start <= 1'b0;
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serirq_mode <= `SERIRQ_MODE_QUIET;
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serirq_mode <= `SERIRQ_MODE_CONTINUOUS;
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end
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end
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4'h4:
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4'h4:
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begin
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begin
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found_stop <= 1'b0;
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found_stop <= 1'b0;
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found_start <= 1'b1;
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found_start <= 1'b1;
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