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[/] [wb_lpc/] [trunk/] [rtl/] [verilog/] [serirq_slave.v] - Diff between revs 11 and 19

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Rev 11 Rev 19
Line 1... Line 1...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  $Id: serirq_slave.v,v 1.1 2008-03-10 14:08:13 hharte Exp $  ////
////  $Id: serirq_slave.v,v 1.2 2008-12-27 19:46:18 hharte Exp $  ////
////  serirq_slave.v - Wishbone Slave to SERIRQ Host Bridge       ////
////  serirq_slave.v - Wishbone Slave to SERIRQ Host Bridge       ////
////                                                              ////
////                                                              ////
////  This file is part of the Wishbone LPC Bridge project        ////
////  This file is part of the Wishbone LPC Bridge project        ////
////  http://www.opencores.org/projects/lpc/                      ////
////  http://www.opencores.org/projects/lpc/                      ////
////                                                              ////
////                                                              ////
Line 162... Line 162...
                case (stop_clk_cnt)
                case (stop_clk_cnt)
                    4'h2:
                    4'h2:
                        begin
                        begin
                            found_stop <= 1'b1;
                            found_stop <= 1'b1;
                            found_start <= 1'b0;
                            found_start <= 1'b0;
                            serirq_mode <= `SERIRQ_MODE_CONTINUOUS;
                            serirq_mode <= `SERIRQ_MODE_QUIET;
                        end
                        end
                    4'h3:
                    4'h3:
                        begin
                        begin
                            found_stop <= 1'b1;
                            found_stop <= 1'b1;
                            found_start <= 1'b0;
                            found_start <= 1'b0;
                            serirq_mode <= `SERIRQ_MODE_QUIET;
                            serirq_mode <= `SERIRQ_MODE_CONTINUOUS;
                        end
                        end
                    4'h4:
                    4'h4:
                        begin
                        begin
                            found_stop <= 1'b0;
                            found_stop <= 1'b0;
                            found_start <= 1'b1;
                            found_start <= 1'b1;

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