URL
https://opencores.org/ocsvn/wb_lpc/wb_lpc/trunk
[/] [wb_lpc/] [trunk/] [rtl/] [verilog/] [wb_dreq_host.v] - Diff between revs 3 and 6
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 3 |
Rev 6 |
| Line 1... |
Line 1... |
//
|
//
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// $Id: wb_dreq_host.v,v 1.1 2008-03-02 20:46:40 hharte Exp $
|
//// $Id: wb_dreq_host.v,v 1.2 2008-03-05 05:50:59 hharte Exp $ ////
|
//// wb_dreq_host.v - Wishbone DMA Controller for LPC Host ////
|
//// wb_dreq_host.v - Wishbone DMA Controller for LPC Host ////
|
//// ////
|
//// ////
|
//// This file is part of the Wishbone LPC Bridge project ////
|
//// This file is part of the Wishbone LPC Bridge project ////
|
//// http://www.opencores.org/projects/wb_lpc/ ////
|
//// http://www.opencores.org/projects/wb_lpc/ ////
|
//// ////
|
//// ////
|
| Line 99... |
Line 99... |
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
|
|
No newline at end of file
|
No newline at end of file
|
© copyright 1999-2025
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.