URL
https://opencores.org/ocsvn/wb_lpc/wb_lpc/trunk
[/] [wb_lpc/] [trunk/] [rtl/] [verilog/] [wb_lpc_defines.v] - Diff between revs 3 and 5
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 3 |
Rev 5 |
| Line 58... |
Line 58... |
`define LPC_ST_P_DATA 13'h040 // LPC Peripheral Data state (2 cycles)
|
`define LPC_ST_P_DATA 13'h040 // LPC Peripheral Data state (2 cycles)
|
`define LPC_ST_H_TAR1 13'h080 // LPC Host Turnaround 1 (Drive LAD 4'hF)
|
`define LPC_ST_H_TAR1 13'h080 // LPC Host Turnaround 1 (Drive LAD 4'hF)
|
`define LPC_ST_H_TAR2 13'h100 // LPC Host Turnaround 2 (Float LAD)
|
`define LPC_ST_H_TAR2 13'h100 // LPC Host Turnaround 2 (Float LAD)
|
`define LPC_ST_P_TAR1 13'h200 // LPC Peripheral Turnaround 1 (Drive LAD = 4'hF)
|
`define LPC_ST_P_TAR1 13'h200 // LPC Peripheral Turnaround 1 (Drive LAD = 4'hF)
|
`define LPC_ST_P_TAR2 13'h400 // LPC Peripheral Turnaround 2 (Float LAD)
|
`define LPC_ST_P_TAR2 13'h400 // LPC Peripheral Turnaround 2 (Float LAD)
|
|
`define LPC_ST_WB_RETIRE 13'h400 // Retire Wishbone transfer (Host only), ends WB cycle.
|
`define LPC_ST_SYNC 13'h800 // LPC Sync State (may be multiple cycles for wait-states)
|
`define LPC_ST_SYNC 13'h800 // LPC Sync State (may be multiple cycles for wait-states)
|
`define LPC_ST_P_WAIT1 13'h1000 // LPC Sync State (may be multiple cycles for wait-states)
|
`define LPC_ST_P_WAIT1 13'h1000 // LPC Sync State (may be multiple cycles for wait-states)
|
|
|
|
|
`define WB_SEL_BYTE 4'b0001 // Byte Transfer
|
`define WB_SEL_BYTE 4'b0001 // Byte Transfer
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.