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Line 1... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// $Id: wb_lpc_host.v,v 1.2 2008-03-05 05:50:25 hharte Exp $ ////
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//// $Id: wb_lpc_host.v,v 1.3 2008-07-22 13:46:42 hharte Exp $ ////
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//// wb_lpc_host.v - Wishbone Slave to LPC Host Bridge ////
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//// wb_lpc_host.v - Wishbone Slave to LPC Host Bridge ////
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//// ////
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//// ////
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//// This file is part of the Wishbone LPC Bridge project ////
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//// This file is part of the Wishbone LPC Bridge project ////
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//// http://www.opencores.org/projects/wb_lpc/ ////
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//// http://www.opencores.org/projects/wb_lpc/ ////
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//// ////
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//// ////
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| Line 163... |
Line 163... |
begin
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begin
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lframe_o <= 1'b0; // In case we came here from a Firmware cycle, which skips CYCTYP.
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lframe_o <= 1'b0; // In case we came here from a Firmware cycle, which skips CYCTYP.
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// The LPC Bus Address is sent across the bus a nibble at a time;
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// The LPC Bus Address is sent across the bus a nibble at a time;
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// however, the most significant nibble is sent first. For firmware and
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// however, the most significant nibble is sent first. For firmware and
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// memory cycles, the address is 32-bits. Actually, for memeory accesses,
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// memory cycles, the address is 32-bits. Actually, for firmware accesses,
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// the most significant nibble is known as the IDSEL field. For I/O,
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// the most significant nibble is known as the IDSEL field. For I/O,
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// the address is only 16-bits wide.
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// the address is only 16-bits wide.
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case(adr_cnt)
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case(adr_cnt)
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3'h0:
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3'h0:
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lad_o <= wbs_adr_i[31:28];
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lad_o <= wbs_adr_i[31:28];
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| Line 269... |
Line 269... |
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dat_cnt <= dat_cnt + 1;
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dat_cnt <= dat_cnt + 1;
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if(nibble_cnt == 1'b1) // end of byte
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if(nibble_cnt == 1'b1) // end of byte
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begin
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begin
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if((fw_xfr) && (byte_cnt != xfr_len-1)) // Firmware transfer does not have TAR between bytes.
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state <= `LPC_ST_H_DATA;
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else
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state <= `LPC_ST_H_TAR1;
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state <= `LPC_ST_H_TAR1;
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end
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end
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else
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else
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state <= `LPC_ST_H_DATA;
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state <= `LPC_ST_H_DATA;
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end
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end
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| Line 326... |
Line 329... |
dat_cnt <= dat_cnt + 1;
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dat_cnt <= dat_cnt + 1;
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if(nibble_cnt == 1'b1) // Byte transfer complete
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if(nibble_cnt == 1'b1) // Byte transfer complete
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if (byte_cnt == xfr_len-1) // End of data transfer phase
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if (byte_cnt == xfr_len-1) // End of data transfer phase
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state <= `LPC_ST_P_TAR1;
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state <= `LPC_ST_P_TAR1;
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else begin
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if(fw_xfr) // Firmware transfer does not have TAR between bytes.
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state <= `LPC_ST_P_DATA;
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else
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else
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state <= `LPC_ST_SYNC;
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state <= `LPC_ST_SYNC;
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end
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else // Go to next nibble
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else // Go to next nibble
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state <= `LPC_ST_P_DATA;
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state <= `LPC_ST_P_DATA;
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end
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end
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`LPC_ST_P_TAR1:
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`LPC_ST_P_TAR1:
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begin
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begin
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