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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// $Id: wb_lpc_host.v,v 1.3 2008-07-22 13:46:42 hharte Exp $ ////
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//// $Id: wb_lpc_host.v,v 1.4 2008-07-26 19:15:31 hharte Exp $ ////
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//// wb_lpc_host.v - Wishbone Slave to LPC Host Bridge ////
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//// wb_lpc_host.v - Wishbone Slave to LPC Host Bridge ////
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//// ////
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//// ////
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//// This file is part of the Wishbone LPC Bridge project ////
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//// This file is part of the Wishbone LPC Bridge project ////
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//// http://www.opencores.org/projects/wb_lpc/ ////
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//// http://www.opencores.org/projects/wb_lpc/ ////
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//// ////
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//// ////
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// 5. H TAR (2) P SYNC (1+) | H TAR (2) +-P SYNC (1+)
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// 5. H TAR (2) P SYNC (1+) | H TAR (2) +-P SYNC (1+)
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// 6. P SYNC (1+) P DATA (2) | H SYNC (1+) +-P DATA (2)
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// 6. P SYNC (1+) P DATA (2) | H SYNC (1+) +-P DATA (2)
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// 7. P TAR (2) P TAR (2) +-P TAR (2) P TAR
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// 7. P TAR (2) P TAR (2) +-P TAR (2) P TAR
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//
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//
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module wb_lpc_host(clk_i, nrst_i, wbs_adr_i, wbs_dat_o, wbs_dat_i, wbs_sel_i, wbs_tga_i, wbs_we_i,
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module wb_lpc_host(clk_i, nrst_i, wbs_adr_i, wbs_dat_o, wbs_dat_i, wbs_sel_i, wbs_tga_i, wbs_we_i,
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wbs_stb_i, wbs_cyc_i, wbs_ack_o,
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wbs_stb_i, wbs_cyc_i, wbs_ack_o, wbs_err_o,
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dma_chan_i, dma_tc_i,
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dma_chan_i, dma_tc_i,
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lframe_o, lad_i, lad_o, lad_oe
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lframe_o, lad_i, lad_o, lad_oe
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);
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);
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// Wishbone Slave Interface
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// Wishbone Slave Interface
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input clk_i;
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input clk_i;
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input [1:0] wbs_tga_i;
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input [1:0] wbs_tga_i;
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input wbs_we_i;
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input wbs_we_i;
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input wbs_stb_i;
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input wbs_stb_i;
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input wbs_cyc_i;
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input wbs_cyc_i;
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output reg wbs_ack_o;
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output reg wbs_ack_o;
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output reg wbs_err_o;
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// LPC Master Interface
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// LPC Master Interface
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output reg lframe_o; // LPC Frame output (active high)
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output reg lframe_o; // LPC Frame output (active high)
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output reg lad_oe; // LPC AD Output Enable
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output reg lad_oe; // LPC AD Output Enable
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input [3:0] lad_i; // LPC AD Input Bus
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input [3:0] lad_i; // LPC AD Input Bus
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// DMA-Specific sideband signals
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// DMA-Specific sideband signals
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input [2:0] dma_chan_i; // DMA Channel
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input [2:0] dma_chan_i; // DMA Channel
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input dma_tc_i; // DMA Terminal Count
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input dma_tc_i; // DMA Terminal Count
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reg [12:0] state; // Current state
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reg [13:0] state; // Current state
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reg [2:0] adr_cnt; // Address nibbe counter
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reg [2:0] adr_cnt; // Address nibbe counter
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reg [3:0] dat_cnt; // Data nibble counter
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reg [3:0] dat_cnt; // Data nibble counter
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reg [2:0] xfr_len; // Number of nibbls for transfer
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reg [2:0] xfr_len; // Number of nibbls for transfer
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wire [2:0] byte_cnt = dat_cnt[3:1]; // Byte Counter
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wire [2:0] byte_cnt = dat_cnt[3:1]; // Byte Counter
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wire nibble_cnt = dat_cnt[0]; // Nibble counter
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wire nibble_cnt = dat_cnt[0]; // Nibble counter
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if(~nrst_i)
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if(~nrst_i)
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begin
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begin
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state <= `LPC_ST_IDLE;
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state <= `LPC_ST_IDLE;
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lframe_o <= 1'b0;
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lframe_o <= 1'b0;
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wbs_ack_o <= 1'b0;
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wbs_ack_o <= 1'b0;
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wbs_err_o <= 1'b0;
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lad_oe <= 1'b0;
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lad_oe <= 1'b0;
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lad_o <= 4'b0;
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lad_o <= 4'b0;
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adr_cnt <= 3'b0;
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adr_cnt <= 3'b0;
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dat_cnt <= 4'h0;
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dat_cnt <= 4'h0;
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xfr_len <= 3'b000;
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xfr_len <= 3'b000;
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else begin
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else begin
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case(state)
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case(state)
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`LPC_ST_IDLE:
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`LPC_ST_IDLE:
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begin
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begin
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wbs_ack_o <= 1'b0;
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wbs_ack_o <= 1'b0;
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wbs_err_o <= 1'b0;
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lframe_o <= 1'b0;
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lframe_o <= 1'b0;
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dat_cnt <= 4'h0;
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dat_cnt <= 4'h0;
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if(wbs_acc) // Wishbone access starts LPC transaction
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if(wbs_acc) // Wishbone access starts LPC transaction
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state <= `LPC_ST_START;
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state <= `LPC_ST_START;
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state <= `LPC_ST_SYNC;
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state <= `LPC_ST_SYNC;
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end
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end
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`LPC_ST_SYNC:
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`LPC_ST_SYNC:
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begin
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begin
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lad_oe <= 1'b0; // float LAD
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lad_oe <= 1'b0; // float LAD
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if(lad_i == `LPC_SYNC_READY) begin
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if((lad_i == `LPC_SYNC_READY) || (lad_i == `LPC_SYNC_MORE)) begin
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if(wbs_wr) begin
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if(wbs_wr) begin
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state <= `LPC_ST_P_TAR1;
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state <= `LPC_ST_P_TAR1;
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end
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end
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else
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else begin
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state <= `LPC_ST_P_DATA;
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state <= `LPC_ST_P_DATA;
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end
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end
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else
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end else if(lad_i == `LPC_SYNC_ERROR) begin
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dat_cnt <= { xfr_len, 1'b1 }; // Terminate data transfer
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wbs_err_o <= 1'b1; // signal wishbone error
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state <= `LPC_ST_P_TAR1;
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end else begin
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state <= `LPC_ST_SYNC;
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state <= `LPC_ST_SYNC;
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end
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end
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end
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`LPC_ST_P_DATA:
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`LPC_ST_P_DATA:
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begin
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begin
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case(dat_cnt)
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case(dat_cnt)
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4'h0:
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4'h0:
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end
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end
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end
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end
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`LPC_ST_WB_RETIRE:
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`LPC_ST_WB_RETIRE:
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begin
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begin
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wbs_ack_o <= 1'b0;
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wbs_ack_o <= 1'b0;
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wbs_err_o <= 1'b0;
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if(wbs_acc) begin
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if(wbs_acc) begin
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state <= `LPC_ST_WB_RETIRE;
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state <= `LPC_ST_WB_RETIRE;
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end
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end
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else begin
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else begin
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state <= `LPC_ST_IDLE;
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state <= `LPC_ST_IDLE;
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