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https://opencores.org/ocsvn/wb_lpc/wb_lpc/trunk
[/] [wb_lpc/] [trunk/] [rtl/] [verilog/] [wb_lpc_host.v] - Diff between revs 3 and 5
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Rev 5 |
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// $Id: wb_lpc_host.v,v 1.1 2008-03-02 20:46:40 hharte Exp $
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//// $Id: wb_lpc_host.v,v 1.2 2008-03-05 05:50:25 hharte Exp $ ////
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//// wb_lpc_host.v - Wishbone Slave to LPC Host Bridge ////
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//// wb_lpc_host.v - Wishbone Slave to LPC Host Bridge ////
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//// ////
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//// ////
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//// This file is part of the Wishbone LPC Bridge project ////
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//// This file is part of the Wishbone LPC Bridge project ////
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//// http://www.opencores.org/projects/wb_lpc/ ////
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//// http://www.opencores.org/projects/wb_lpc/ ////
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//// ////
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//// ////
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state <= `LPC_ST_P_DATA;
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state <= `LPC_ST_P_DATA;
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end
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end
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`LPC_ST_P_TAR1:
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`LPC_ST_P_TAR1:
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begin
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begin
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lad_oe <= 1'b0;
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lad_oe <= 1'b0;
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// state <= `LPC_ST_P_TAR2;
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// end
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// `LPC_ST_P_TAR2:
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// begin
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// lad_oe <= 1'b0; // float LAD
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if(byte_cnt == xfr_len) begin
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if(byte_cnt == xfr_len) begin
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state <= `LPC_ST_IDLE;
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state <= `LPC_ST_WB_RETIRE;
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wbs_ack_o <= wbs_acc;
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wbs_ack_o <= wbs_acc;
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end
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end
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else begin
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else begin
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if(wbs_wr) begin // DMA READ (Host to Peripheral)
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if(wbs_wr) begin // DMA READ (Host to Peripheral)
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state <= `LPC_ST_H_DATA;
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state <= `LPC_ST_H_DATA;
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Line 347... |
else begin // unhandled READ case
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else begin // unhandled READ case
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state <= `LPC_ST_IDLE;
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state <= `LPC_ST_IDLE;
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end
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end
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end
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end
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end
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end
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`LPC_ST_WB_RETIRE:
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begin
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wbs_ack_o <= 1'b0;
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if(wbs_acc) begin
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state <= `LPC_ST_WB_RETIRE;
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end
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else begin
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state <= `LPC_ST_IDLE;
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end
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end
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endcase
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endcase
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end
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end
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endmodule
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endmodule
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