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https://opencores.org/ocsvn/wb_lpc/wb_lpc/trunk
[/] [wb_lpc/] [trunk/] [rtl/] [verilog/] [wb_lpc_periph.v] - Diff between revs 6 and 15
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| Rev 6 |
Rev 15 |
| Line 1... |
Line 1... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// $Id: wb_lpc_periph.v,v 1.2 2008-03-05 05:50:59 hharte Exp $ ////
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//// $Id: wb_lpc_periph.v,v 1.3 2008-07-22 13:46:42 hharte Exp $ ////
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//// wb_lpc_periph.v - LPC Peripheral to Wishbone Master Bridge ////
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//// wb_lpc_periph.v - LPC Peripheral to Wishbone Master Bridge ////
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//// ////
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//// ////
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//// This file is part of the Wishbone LPC Bridge project ////
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//// This file is part of the Wishbone LPC Bridge project ////
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//// http://www.opencores.org/projects/wb_lpc/ ////
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//// http://www.opencores.org/projects/wb_lpc/ ////
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//// ////
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//// ////
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| Line 283... |
Line 283... |
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dat_cnt <= dat_cnt + 1;
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dat_cnt <= dat_cnt + 1;
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if(nibble_cnt == 1'b1) // end of byte
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if(nibble_cnt == 1'b1) // end of byte
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begin
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begin
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if((fw_xfr) && (byte_cnt != xfr_len-1)) // Firmware transfer does not have TAR between bytes.
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state <= `LPC_ST_H_DATA;
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else
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state <= `LPC_ST_H_TAR1;
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state <= `LPC_ST_H_TAR1;
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end
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end
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else
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else
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state <= `LPC_ST_H_DATA;
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state <= `LPC_ST_H_DATA;
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| Line 363... |
Line 366... |
dat_cnt <= dat_cnt + 1;
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dat_cnt <= dat_cnt + 1;
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if(nibble_cnt == 1'b1) // Byte transfer complete
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if(nibble_cnt == 1'b1) // Byte transfer complete
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if (byte_cnt == xfr_len-1) // Byte transfer complete
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if (byte_cnt == xfr_len-1) // Byte transfer complete
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state <= `LPC_ST_P_TAR1;
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state <= `LPC_ST_P_TAR1;
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else begin
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if(fw_xfr) // Firmware transfer does not have TAR between bytes.
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state <= `LPC_ST_P_DATA;
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else
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else
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state <= `LPC_ST_SYNC;
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state <= `LPC_ST_SYNC;
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end
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else
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else
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state <= `LPC_ST_P_DATA;
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state <= `LPC_ST_P_DATA;
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lad_oe <= 1'b1;
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lad_oe <= 1'b1;
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end
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end
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