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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// $Id: wb_lpc_periph.v,v 1.1 2008-03-02 20:46:40 hharte Exp $
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//// $Id: wb_lpc_periph.v,v 1.2 2008-03-05 05:50:59 hharte Exp $ ////
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//// wb_lpc_periph.v - LPC Peripheral to Wishbone Master Bridge ////
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//// wb_lpc_periph.v - LPC Peripheral to Wishbone Master Bridge ////
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//// ////
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//// ////
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//// This file is part of the Wishbone LPC Bridge project ////
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//// This file is part of the Wishbone LPC Bridge project ////
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//// http://www.opencores.org/projects/wb_lpc/ ////
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//// http://www.opencores.org/projects/wb_lpc/ ////
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//// ////
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//// ////
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// DMA-Specific sideband signals
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// DMA-Specific sideband signals
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output [2:0] dma_chan_o; // DMA Channel
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output [2:0] dma_chan_o; // DMA Channel
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output dma_tc_o; // DMA Terminal Count
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output dma_tc_o; // DMA Terminal Count
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reg [12:0] state; // Current state
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reg [12:0] state; // Current state
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reg [2:0] adr_cnt; // Address nibbe counter
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reg [2:0] adr_cnt; // Address nibble counter
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reg [3:0] dat_cnt; // Data nibble counter
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reg [3:0] dat_cnt; // Data nibble counter
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wire [2:0] byte_cnt = dat_cnt[3:1]; // Byte counter
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wire [2:0] byte_cnt = dat_cnt[3:1]; // Byte counter
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wire nibble_cnt = dat_cnt[0]; // Nibble counter
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wire nibble_cnt = dat_cnt[0]; // Nibble counter
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reg [31:0] lpc_dat_i; // Temporary storage for input data.
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reg [31:0] lpc_dat_i; // Temporary storage for input data.
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lad_o <= lpc_dat_i[31:28];
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lad_o <= lpc_dat_i[31:28];
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endcase
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endcase
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dat_cnt <= dat_cnt + 1;
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dat_cnt <= dat_cnt + 1;
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// if(nibble_cnt == 1'b1)
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// state <= `LPC_ST_P_TAR1;
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if(nibble_cnt == 1'b1) // Byte transfer complete
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if(nibble_cnt == 1'b1) // Byte transfer complete
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if (byte_cnt == xfr_len-1) // Byte transfer complete
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if (byte_cnt == xfr_len-1) // Byte transfer complete
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state <= `LPC_ST_P_TAR1;
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state <= `LPC_ST_P_TAR1;
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else
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else
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state <= `LPC_ST_SYNC;
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state <= `LPC_ST_SYNC;
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end
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end
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endmodule
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endmodule
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