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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// $Id: wb_regfile.v,v 1.1 2008-03-02 20:46:40 hharte Exp $
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//// $Id: wb_regfile.v,v 1.2 2008-03-05 05:50:59 hharte Exp $ ////
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//// wb_regfile.v - Small Wishbone register file for testing ////
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//// wb_regfile.v - Small Wishbone register file for testing ////
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//// ////
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//// ////
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//// This file is part of the Wishbone LPC Bridge project ////
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//// This file is part of the Wishbone LPC Bridge project ////
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//// http://www.opencores.org/projects/wb_lpc/ ////
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//// http://www.opencores.org/projects/wb_lpc/ ////
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//// ////
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//// ////
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// case (wb_adr_i) // synopsys full_case parallel_case
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// case (wb_adr_i) // synopsys full_case parallel_case
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// 3'b000: {datareg0_3, datareg0_2, datareg0_1, datareg0_0} <= wb_dat_i[31:0];
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// 3'b000: {datareg0_3, datareg0_2, datareg0_1, datareg0_0} <= wb_dat_i[31:0];
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// endcase
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// endcase
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endcase
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endcase
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//
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// generate dat_o
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// generate dat_o
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always @(posedge clk_i)
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always @(posedge clk_i)
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case (wb_sel_i)
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case (wb_sel_i)
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4'b0000:
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4'b0000:
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case (wb_adr_i) // synopsys full_case parallel_case
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case (wb_adr_i) // synopsys full_case parallel_case
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wb_dat_o[15:0] <= {datareg0_1, datareg0_0};
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wb_dat_o[15:0] <= {datareg0_1, datareg0_0};
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4'b1111:
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4'b1111:
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wb_dat_o[31:0] <= {datareg0_3, datareg0_2, datareg0_1, datareg0_0};
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wb_dat_o[31:0] <= {datareg0_3, datareg0_2, datareg0_1, datareg0_0};
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endcase
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endcase
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//
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// generate ack_o
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// generate ack_o
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always @(posedge clk_i)
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always @(posedge clk_i)
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wb_ack_o <= #1 wb_acc & !wb_ack_o;
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wb_ack_o <= #1 wb_acc & !wb_ack_o;
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assign datareg0 = { datareg0_3, datareg0_2, datareg0_1, datareg0_0 };
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assign datareg0 = { datareg0_3, datareg0_2, datareg0_1, datareg0_0 };
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