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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// MCS51 to Wishbone Interface ////
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//// MCS51 to Wishbone Interface ////
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//// ////
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//// ////
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//// $Id: wb_mcs51.v,v 1.1 2008-03-03 15:54:43 hharte Exp $ ////
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//// $Id: wb_mcs51.v,v 1.2 2008-03-10 13:58:10 hharte Exp $ ////
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//// ////
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//// ////
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//// Copyright (C) 2007 Howard M. Harte ////
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//// Copyright (C) 2007 Howard M. Harte ////
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//// hharte@opencores.org ////
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//// hharte@opencores.org ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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module wb_mcs51 (nrst_i, clk_i, mcs51_ale, mcs51_rd, mcs51_wr, mcs51_ad_inout,
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module wb_mcs51 (nrst_i, clk_i, mcs51_ale, mcs51_rd, mcs51_wr, mcs51_ad_inout,
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wbm_adr_o, wbm_dat_i, wbm_dat_o, wbm_sel_o, wbm_cyc_o,
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wbm_adr_o, wbm_dat_i, wbm_dat_o, wbm_sel_o, wbm_cyc_o,
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wbm_stb_o, wbm_we_o, wbm_ack_i, wbm_rty_i, wbm_err_i);
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wbm_stb_o, wbm_we_o, wbm_ack_i, wbm_rty_i, wbm_err_i);
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parameter mcs51_aw = 8 ;
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parameter wb_aw = 16;
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input nrst_i;
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input nrst_i;
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input clk_i;
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input clk_i;
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input mcs51_ale;
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input mcs51_ale;
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input mcs51_rd;
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input mcs51_rd;
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input mcs51_wr;
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input mcs51_wr;
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inout [7:0] mcs51_ad_inout;
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inout [mcs51_aw-1:0] mcs51_ad_inout;
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// Wishbone master interface
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// WISHBONE master interface
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output [15:0] wbm_adr_o;
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output [wb_aw-1:0] wbm_adr_o;
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input [7:0] wbm_dat_i;
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input [7:0] wbm_dat_i;
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output [7:0] wbm_dat_o;
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output [7:0] wbm_dat_o;
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output wbm_sel_o;
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output wbm_sel_o;
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output wbm_cyc_o;
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output wbm_cyc_o;
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output wbm_stb_o;
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output wbm_stb_o;
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input wbm_err_i;
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input wbm_err_i;
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wire l_wbm_stb;
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wire l_wbm_stb;
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wire mcs51_ad_oe;
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wire mcs51_ad_oe;
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reg [15:0] mcs51_addr;
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reg [mcs51_aw-1:0] mcs51_addr;
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always @(negedge mcs51_ale or negedge nrst_i)
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always @(negedge mcs51_ale or negedge nrst_i)
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if (~nrst_i)
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if (~nrst_i)
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begin
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begin
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mcs51_addr <= 16'h0000;
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mcs51_addr <= {{wb_aw}{1'b0}};
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end
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end
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else if(~mcs51_ale) // Latch address
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else if(~mcs51_ale) // Latch address
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mcs51_addr <= { 8'h0 , mcs51_ad_inout };
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mcs51_addr <= { {{16-mcs51_aw}{1'b0}} , mcs51_ad_inout[mcs51_aw-1:0] };
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assign mcs51_ad_oe = ~mcs51_rd;
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assign mcs51_ad_oe = ~mcs51_rd;
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assign wbm_adr_o = mcs51_addr;
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assign wbm_adr_o = { {{wb_aw-16}{1'b0}}, mcs51_addr };
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assign wbm_we_o = ~mcs51_wr;
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assign wbm_we_o = ~mcs51_wr;
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assign wbm_stb_o = ~mcs51_wr | ~mcs51_rd;
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assign wbm_stb_o = ~mcs51_wr | ~mcs51_rd;
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assign wbm_cyc_o = wbm_stb_o;
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assign wbm_cyc_o = wbm_stb_o;
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assign mcs51_ad_inout = mcs51_ad_oe ? wbm_dat_i : 8'bzzzzzzzz;
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assign mcs51_ad_inout = mcs51_ad_oe ? wbm_dat_i : 8'bzzzzzzzz;
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assign wbm_sel_o = wbm_stb_o;
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assign wbm_sel_o = wbm_stb_o;
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assign wbm_dat_o = mcs51_ad_inout;
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assign wbm_dat_o = mcs51_ad_inout[7:0];
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assign wmb_sel_o = 4'b0001;
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endmodule
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endmodule
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