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--
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-- Technology mapping library. Interface.
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--
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-- (c) Copyright Andras Tantos <andras_tantos@yahoo.com> 2001/03/31
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-- This code is distributed under the terms and conditions of the GNU General Public Lince.
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--
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library IEEE;
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use IEEE.std_logic_1164.all;
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package technology is
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-- originaly in synopsys. Naming convention is changed to resolve potential name conflict.
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function to_std_logic_vector(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR;
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function to_integer(arg:std_logic_vector) return integer;
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-- function add_one(inp : std_logic_vector) return std_logic_vector;
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-- function sub_one(inp : std_logic_vector) return std_logic_vector;
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function is_zero(inp : std_logic_vector) return boolean;
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function sl(l: std_logic_vector; r: integer) return std_logic_vector;
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function sr(l: std_logic_vector; r: integer) return std_logic_vector;
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-- function "+"(op_l, op_r: std_logic_vector) return std_logic_vector;
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-- function "-"(op_l, op_r: std_logic_vector) return std_logic_vector;
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function log2(inp : integer) return integer;
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function bus_resize2adr_bits(in_bus : integer; out_bus: integer) return integer;
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function size2bits(inp : integer) return integer;
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function max2(a : integer; b: integer) return integer;
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function min2(a : integer; b: integer) return integer;
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function equ(a : std_logic_vector; b : integer) return boolean;
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component d_ff
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port (
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d : in STD_LOGIC;
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clk: in STD_LOGIC;
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ena: in STD_LOGIC := '1';
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clr: in STD_LOGIC := '0';
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pre: in STD_LOGIC := '0';
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q : out STD_LOGIC
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);
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end component;
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component spmem
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generic (
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default_out : std_logic := 'X'; -- Default output
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default_content : std_logic := '0'; -- Simple initialization data
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adr_width : integer := 3;
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dat_width : integer := 8;
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async_read : boolean := true
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);
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port (
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stb_i : std_logic; -- chip select
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clk_i : in std_logic; -- write clock
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adr_i : in std_logic_vector(adr_width -1 downto 0); -- Address
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dat_i : in std_logic_vector(dat_width -1 downto 0); -- input data
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dat_o : out std_logic_vector(dat_width -1 downto 0); -- Output Data
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we_i : in std_logic; -- Read Write Enable
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ack_o : out std_logic -- Ready output
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);
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end component;
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component dpmem
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generic (
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default_out : std_logic := 'X'; -- Default output
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default_content : std_logic := '0'; -- Simple initialization data
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adr_width : integer := 3;
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dat_width : integer := 8;
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async_read : boolean := true
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);
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port (
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-- Signals for the port A
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a_clk_i : in std_logic; -- Read clock
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a_stb_i : in std_logic; -- Read port select
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a_we_i : in std_logic; -- Read port Write enable
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a_adr_i : in std_logic_vector(adr_width -1 downto 0); -- Read Address
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a_dat_i : in std_logic_vector(dat_width -1 downto 0); -- Input data
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a_dat_o : out std_logic_vector(dat_width -1 downto 0); -- Output data
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a_ack_o : out std_logic; -- Read ready output
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-- Signals for the port B
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b_clk_i : in std_logic; -- Write clock
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b_stb_i : in std_logic; -- Write port select
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b_we_i : in std_logic; -- Write Enable
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b_adr_i : in std_logic_vector(adr_width -1 downto 0); -- Write Address
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b_dat_i : in std_logic_vector(dat_width -1 downto 0); -- Input data
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b_dat_o : out std_logic_vector(dat_width -1 downto 0); -- Output data
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b_ack_o : out std_logic -- Write ready output
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);
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end component;
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component fifo
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generic (
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default_out : std_logic := 'X'; -- Default output
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default_content : std_logic := '0'; -- Simple initialization data
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adr_width : integer := 3;
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dat_width : integer := 8;
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async_read : boolean := true -- Controls memory only. For FIFO logic clock is still needed.
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);
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port (
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reset : in std_logic; -- System reset
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r_clk_i : in std_logic; -- Read clock
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r_stb_i : in std_logic; -- Read port select
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r_we_i : in std_logic := '0'; -- Read port Write enable (should be '0')
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r_dat_o : out std_logic_vector(dat_width-1 downto 0); -- Data out
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r_ack_o : out std_logic; -- Read ready output
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w_clk_i : in std_logic; -- Write clock
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w_stb_i : in std_logic; -- Write port select
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w_we_i : in std_logic := '1'; -- Write port write enable
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w_dat_i : in std_logic_vector(dat_width-1 downto 0); -- Data in
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w_ack_o : out std_logic; -- Write ready output
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full_o : out std_logic; -- Full Flag (combinational)
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empty_o : out std_logic; -- Empty flag (combinational)
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used_o : out std_logic_vector(adr_width downto 0) -- number of data in the fifo (combinational)
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);
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end component;
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end technology;
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity spmem is
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generic (
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default_out : std_logic := 'X'; -- Default output
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default_content : std_logic := '0'; -- Simple initialization data
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adr_width : integer := 3;
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dat_width : integer := 8;
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async_read : boolean := true
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);
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port (
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stb_i : std_logic; -- chip select
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clk_i : in std_logic; -- write clock
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adr_i : in std_logic_vector(adr_width -1 downto 0); -- Address
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dat_i : in std_logic_vector(dat_width -1 downto 0); -- input data
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dat_o : out std_logic_vector(dat_width -1 downto 0); -- Output Data
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we_i : in std_logic; -- Read Write Enable
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ack_o : out std_logic -- Ready output
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);
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end spmem;
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity dpmem is
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generic (
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default_out : std_logic := 'X'; -- Default output
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default_content : std_logic := '0'; -- Simple initialization data
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adr_width : integer := 3;
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dat_width : integer := 8;
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async_read : boolean := true
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);
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port (
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-- Signals for the port A
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a_clk_i : in std_logic; -- Read clock
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a_stb_i : in std_logic; -- Read port select
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a_we_i : in std_logic; -- Read port Write enable
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a_adr_i : in std_logic_vector(adr_width -1 downto 0); -- Read Address
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a_dat_i : in std_logic_vector(dat_width -1 downto 0); -- Input data
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a_dat_o : out std_logic_vector(dat_width -1 downto 0); -- Output data
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a_ack_o : out std_logic; -- Read ready output
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-- Signals for the port B
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b_clk_i : in std_logic; -- Write clock
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b_stb_i : in std_logic; -- Write port select
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b_we_i : in std_logic; -- Write Enable
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b_adr_i : in std_logic_vector(adr_width -1 downto 0); -- Write Address
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b_dat_i : in std_logic_vector(dat_width -1 downto 0); -- Input data
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b_dat_o : out std_logic_vector(dat_width -1 downto 0); -- Output data
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b_ack_o : out std_logic -- Write ready output
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);
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end dpmem;
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity fifo is
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generic (
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default_out : std_logic := 'X'; -- Default output
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default_content : std_logic := '0'; -- Simple initialization data
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adr_width : integer := 3;
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dat_width : integer := 8;
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async_read : boolean := true -- Controls memory only. For FIFO logic clock is still needed.
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);
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port (
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reset : in std_logic; -- System reset
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r_clk_i : in std_logic; -- Read clock
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r_stb_i : in std_logic; -- Read port select
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r_we_i : in std_logic := '0'; -- Read port Write enable (should be '0')
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r_dat_o : out std_logic_vector(dat_width-1 downto 0); -- Data out
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r_ack_o : out std_logic; -- Read ready output
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w_clk_i : in std_logic; -- Write clock
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w_stb_i : in std_logic; -- Write port select
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w_we_i : in std_logic := '1'; -- Write port write enable
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w_dat_i : in std_logic_vector(dat_width-1 downto 0); -- Data in
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w_ack_o : out std_logic; -- Write ready output
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full_o : out std_logic; -- Full Flag (combinational)
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empty_o : out std_logic; -- Empty flag (combinational)
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used_o : out std_logic_vector(adr_width downto 0) -- number of data in the fifo (combinational)
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);
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end fifo;
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity d_ff is
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port (
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d : in STD_LOGIC;
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clk: in STD_LOGIC;
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ena: in STD_LOGIC := '1';
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clr: in STD_LOGIC := '0';
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pre: in STD_LOGIC := '0';
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q : out STD_LOGIC
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);
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end d_ff;
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