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// -*- Mode: Verilog -*-
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// Filename : wb_master.v
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// Description : Wishbone Master Behavorial
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// Author : Winefred Washington
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// Created On : Thu Jan 11 21:18:41 2001
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// Last Modified By: .
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// Last Modified On: .
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// Update Count : 0
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// Status : Unknown, Use with caution!
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// Description Specification
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// General Description: 8, 16, 32-bit WISHBONE Master
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// Supported cycles: MASTER, READ/WRITE
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// MASTER, BLOCK READ/WRITE
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// MASTER, RMW
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// Data port, size: 8, 16, 32-bit
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// Data port, granularity 8-bit
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// Data port, Max. operand size 32-bit
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// Data transfer ordering: little endian
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// Data transfer sequencing: undefined
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//
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module WB_MASTER32(CLK_I, RST_I, TAG_I, TAG_O,
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ACK_I, ADR_O, CYC_O, DAT_I, DAT_O, ERR_I, RTY_I, SEL_O, STB_O, WE_O);
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input CLK_I;
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input RST_I;
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input [3:0] TAG_I;
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output [3:0] TAG_O;
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input ACK_I;
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output [31:0] ADR_O;
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output CYC_O;
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input [31:0] DAT_I;
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output [31:0] DAT_O;
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input ERR_I;
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input RTY_I;
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output [3:0] SEL_O;
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output STB_O;
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output WE_O;
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reg [31:0] ADR_O;
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reg [3:0] SEL_O;
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reg CYC_O;
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reg STB_O;
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reg WE_O;
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reg [31:0] DAT_O;
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wire [15:0] mem_sizes; // determines the data width of an address range
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reg [31:0] write_burst_buffer[0:7];
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reg [31:0] read_burst_buffer[0:7];
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reg GO;
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integer cycle_end;
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integer address;
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integer data;
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integer selects;
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integer write_flag;
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//
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// mem_sizes determines the data widths of memory space
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// The memory space is divided into eight regions. Each
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// region is controlled by a two bit field.
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//
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// Bits
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// 00 = 8 bit memory space
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// 01 = 16 bit
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// 10 = 32 bit
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// 11 = 64 bit (not supported in this model
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//
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assign mem_sizes = 16'b00_01_10_11_00_01_10_11;
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function [1:0] data_width;
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input [31:0] adr;
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begin
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casex (adr[31:29])
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3'b000: data_width = mem_sizes[15:14];
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3'b001: data_width = mem_sizes[13:12];
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3'b010: data_width = mem_sizes[11:10];
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3'b011: data_width = mem_sizes[9:8];
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3'b100: data_width = mem_sizes[7:6];
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3'b101: data_width = mem_sizes[5:4];
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3'b110: data_width = mem_sizes[3:2];
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3'b111: data_width = mem_sizes[1:0];
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3'bxxx: data_width = 2'bxx;
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endcase // casex (adr[31:29])
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end
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endfunction
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always @(posedge CLK_I or posedge RST_I)
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begin
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if (RST_I)
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begin
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GO = 1'b0;
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end
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end
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// read single
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task rd;
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input [31:0] adr;
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output [31:0] result;
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begin
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cycle_end = 1;
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address = adr;
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selects = 255;
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write_flag = 0;
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GO <= 1;
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@(posedge CLK_I);
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GO <= 0;
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// wait for cycle to start
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while (~CYC_O)
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@(posedge CLK_I);
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// wait for cycle to end
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while (CYC_O)
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@(posedge CLK_I);
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result = data;
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end
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endtask // read
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task wr;
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input [31:0] adr;
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input [31:0] dat;
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input [3:0] sel;
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begin
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cycle_end = 1;
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address = adr;
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selects = sel;
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write_flag = 1;
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data = dat;
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GO <= 1;
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@(posedge CLK_I);
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GO <= 0;
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// wait for cycle to start
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while (~CYC_O)
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@(posedge CLK_I);
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// wait for cycle to end
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while (CYC_O)
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@(posedge CLK_I);
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end
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endtask // wr
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// block read
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task blkrd;
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input [31:0] adr;
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input end_flag;
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output [31:0] result;
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begin
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write_flag = 0;
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cycle_end = end_flag;
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address = adr;
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GO <= 1;
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@(posedge CLK_I);
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GO <= 0;
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while (~(ACK_I & STB_O))
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@(posedge CLK_I);
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result = data;
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end
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endtask // blkrd
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// block write
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task blkwr;
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input [31:0] adr;
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input [31:0] dat;
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input [3:0] sel;
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input end_flag;
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begin
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write_flag = 1;
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cycle_end = end_flag;
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address = adr;
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data = dat;
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selects = sel;
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GO <= 1;
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@(posedge CLK_I);
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GO <= 0;
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while (~(ACK_I & STB_O))
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@(posedge CLK_I);
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end
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endtask // blkwr
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// RMW
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task rmw;
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input [31:0] adr;
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input [31:0] dat;
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input [3:0] sel;
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output [31:0] result;
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begin
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// read phase
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write_flag = 0;
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cycle_end = 0;
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address = adr;
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GO <= 1;
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@(posedge CLK_I);
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GO <= 0;
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while (~(ACK_I & STB_O))
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@(posedge CLK_I);
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result = data;
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// write phase
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write_flag = 1;
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address = adr;
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selects = sel;
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GO <= 1;
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data <= dat;
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cycle_end <= 1;
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@(posedge CLK_I);
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GO <= 0;
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while (~(ACK_I & STB_O))
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@(posedge CLK_I);
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end
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endtask // rmw
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always @(posedge CLK_I)
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begin
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if (RST_I)
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ADR_O <= 32'h0000_0000;
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else
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ADR_O <= address;
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end
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always @(posedge CLK_I)
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begin
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if (RST_I | ERR_I | RTY_I)
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CYC_O <= 1'b0;
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else if ((cycle_end == 1) & ACK_I)
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CYC_O <= 1'b0;
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else if (GO | CYC_O)
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CYC_O <= 1'b1;
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end
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// stb control
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always @(posedge CLK_I)
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begin
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if (RST_I | ERR_I | RTY_I)
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STB_O <= 1'b0;
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else if (STB_O & ACK_I)
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STB_O <= 1'b0;
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else if (GO | STB_O)
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STB_O <= 1'b1;
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end
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// selects & data
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always @(posedge CLK_I)
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begin
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if (write_flag == 0) begin
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SEL_O <= 4'b1111;
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if (STB_O & ACK_I)
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data <= DAT_I;
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end
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else begin
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case (data_width(address))
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2'b00: begin
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SEL_O <= {3'b000, selects[0]};
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DAT_O <= {data[7:0], data[7:0], data[7:0], data[7:0]};
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end
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2'b01: begin
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SEL_O <= {2'b00, selects[1:0]};
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DAT_O <= {data[15:0], data[15:0]};
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end
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2'b10: begin
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SEL_O <= selects;
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DAT_O <= data;
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end
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endcase
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end
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end
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always @(posedge CLK_I)
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begin
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if (RST_I)
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WE_O <= 1'b0;
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else if (GO)
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WE_O <= write_flag;
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end
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endmodule
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