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[/] [wb_z80/] [trunk/] [asm/] [BJS80TST.ASM] - Diff between revs 26 and 30

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Rev 26	Rev 30
Line 1...	Line 1...
`; bjp modified to assemble on as80.`	`; bjp modified to assemble on as80 assembler (needs different syntax).`
`; minor mods to account for changes in interrupt structure and I/O`	`; minor mods to account for changes in interrupt structure and I/O`
`; all such are flagged with my initials.....`	`; all such are flagged with my initials.....`
`;`	`;`
`; The origional code used operators < and > on symbols to extract the`	`; The origional code used operators < and > on symbols to extract the`
`; lower and higher bytes respectively. It appears that as80 has no equivaltent.`	`; lower and higher bytes respectively. It appears that as80 has no equivalent.`
`; I have hand coded such ---- hopefully correctly.`	`; I have hand coded such ---- hopefully correctly.`
`; This is only a significant issue with such constructs as`	`; This is only a significant issue with such constructs as`
`; My solution forces the stack to remain in its present location.`	`; My solution forces the stack to remain in its present location.`
`;`	`;`
`; WARNING If you must move the stack -- check comments and fix code for my kludges`	`; WARNING If you must move the stack -- check comments and fix code for my kludges`
`;`	`;`
	`; Origional Code also had a pretty strange "passed" macro. Removed it and`
	`; output a more useful message. along with the bist controls`
	`;`
`;z80 simulator test routine`	`;z80 simulator test routine`
`;total error count is left in a at end of test routine`	`;total error count is left in a at end of test routine`
`;`	`;`

`code`	`code`
Line 55...	Line 58...
`ret`	`ret`
`;`	`;`
`code`	`code`
`;`	`;`

`fail: db 'failed'`	`in_port: equ #20`
`pass: db 'passed'`	`out_port: equ #20`
`message_addr: equ #be58`	`bist_adr: equ #ffff ;last memory address for bist controll register`
`in_port: equ #10`	`bist_ack: equ #01`
`out_port: equ #10`	`bist_err: equ #02`
	`bist_ei: equ #04 ;interrupt enable register for bist`
`;`	`;`
`data_55: equ #55`	`data_55: equ #55`
`data_7f: equ #7f`	`data_7f: equ #7f`
`data_80: equ #80`	`data_80: equ #80`
`data_aa: equ #aa`	`data_aa: equ #aa`
Line 73...	Line 77...
`data_55aa: equ #55aa`	`data_55aa: equ #55aa`
`data_7fff: equ #7fff`	`data_7fff: equ #7fff`
`data_8000: equ #8000`	`data_8000: equ #8000`
`data_aa55: equ #aa55`	`data_aa55: equ #aa55`
`data_ffff: equ #ffff`	`data_ffff: equ #ffff`
	`cr: equ #0d`
	`lf: equ #0a`
	`bell: equ #07`
`;`	`;`
`;inc_error_cnt macro ;bjp change for initial test to halt on error`	`;inc_error_cnt macro ;bjp change for initial test to halt on error`
`; ld hl,error_cnt`	`; ld hl,error_cnt`
`; inc (hl)`	`; inc (hl)`
`; endm`	`; endm`
`inc_error_cnt macro`	`inc_error_cnt macro`
`halt`	`halt`
`endm`	`endm`

`;`	`;`
`passed macro`	`;passed macro`
`push bc`	`; push bc`
`ld bc,(pass)`	`; ld bc,(pass)`
`ld (message_addr),bc`	`; ld (message_addr),bc`
`ld bc,(pass+2)`	`; ld bc,(pass+2)`
`ld (message_addr+2),bc`	`; ld (message_addr+2),bc`
`ld bc,(pass+4)`	`; ld bc,(pass+4)`
`ld (message_addr+4),bc`	`; ld (message_addr+4),bc`
`pop bc`	`; pop bc`
`endm`	`; endm`
`;`	`;`
`failed macro`	`;failed macro`
`push bc`	`; push bc`
`ld bc,(fail)`	`; ld bc,(fail)`
`ld (message_addr),bc`	`; ld (message_addr),bc`
`ld bc,(fail+2)`	`; ld bc,(fail+2)`
`ld (message_addr+2),bc`	`; ld (message_addr+2),bc`
`ld bc,(fail+4)`	`; ld bc,(fail+4)`
`ld (message_addr+4),bc`	`; ld (message_addr+4),bc`
`pop bc`	`; pop bc`
`endm`	`; endm`
`;`	`;`
`;`	`;`

`start: xor a`	`start: xor a`
`ld (pass_count),a`	`ld (pass_count),a`
`ld hl,error_cnt`	`ld hl,error_cnt`
`ld (hl),a ;clear error count`	`ld (hl),a ;clear error count`
`nop_1: nop`	`nop_1: nop`
`nop`	`nop`

`ld_167: ld a,data_55`	`ld_167: ld a,data_55`
`cp data_55`	`cp data_55`
`jr z,ld_1`	`jr z,ld_1`
`inc_error_cnt`	`inc_error_cnt`
`ld_1: ld b,data_7f`	`ld_1: ld b,data_7f`
Line 3720...	Line 3728...
`inc_error_cnt`	`inc_error_cnt`
`dec_57: ld a,e`	`dec_57: ld a,e`
`cp a,#54 ;`	`cp a,#54 ;`
`jr z,rlca_0`	`jr z,rlca_0`
`inc_error_cnt`	`inc_error_cnt`
`rlca_0: ld a,data_80`	`; bjp don't see any further mucking with sp after the load above.`
	`; perhaps it is now safe to enable interrupts. and test them a little`
	`rlca_0: ld hl, bist_adr ; enable interrupts`
	`ld (hl), bist_ei`
	`ld a, #72 ;bjp this is >int_tbl - if you move int_tbl change`
	`ld i, a`
	`ei`

	`ld a,data_80`
`rlca`	`rlca`
`jr c,rlca_1`	`jr c,rlca_1`
`inc_error_cnt`	`inc_error_cnt`
`rlca_1: rlca`	`rlca_1: rlca`
`jr nc,rlca_2`	`jr nc,rlca_2`
Line 3752...	Line 3768...
`rla_3: ld a,data_7f`	`rla_3: ld a,data_7f`
`rla`	`rla`
`cp a,data_ff-1`	`cp a,data_ff-1`
`jr z,rrca_0`	`jr z,rrca_0`
`inc_error_cnt`	`inc_error_cnt`
`rrca_0: scf`	`rrca_0: di ; disable interrupts we want to enable at specific pts`
	`scf`
`ccf`	`ccf`
`ld a,1`	`ld a,1`
`rrca`	`rrca`
`jr c,rrca_1`	`jr c,rrca_1`
`inc_error_cnt`	`inc_error_cnt`
Line 5834...	Line 5851...
`jr z,ldir_0`	`jr z,ldir_0`
`inc_error_cnt`	`inc_error_cnt`
`ldir_0: ld hl,var1`	`ldir_0: ld hl,var1`
`ld de,t_var1`	`ld de,t_var1`
`ld bc,5`	`ld bc,5`
	`ei ;bjp be sure we can interrupt this instruction`
`ldir`	`ldir`
`jp po,ldir_1`	`jp po,ldir_1`
`inc_error_cnt`	`inc_error_cnt`
`ldir_1: ld hl,t_var1`	`ldir_1: ld hl,t_var1`
`ld a,(hl)`	`ld a,(hl)`
Line 6079...	Line 6097...
`cpdr_10: jp m,out_0`	`cpdr_10: jp m,out_0`
`inc_error_cnt`	`inc_error_cnt`
`;`	`;`
`;the file portfe.xxx must be examined to see if the proper output is generated`	`;the file portfe.xxx must be examined to see if the proper output is generated`
`;`	`;`
`out_0: ld a,#30`	`out_0: di ; interrupts are tested, don't muck up output`
	`ld a,#30`
`out (out_port),a`	`out (out_port),a`
`ld c,out_port`	`ld c,out_port`
`ld a,#31`	`ld a,#31`
`out (c),a`	`out (c),a`
`ld b,#32`	`ld b,#32`
Line 6136...	Line 6155...
`ld (pass_count),a`	`ld (pass_count),a`
`ld hl,error_cnt`	`ld hl,error_cnt`
`ld a,(hl)`	`ld a,(hl)`
`cp a,0`	`cp a,0`
`jr z,worked`	`jr z,worked`
`failed`	`failed: ld hl,fail_msg`
`cp a,0`	`ld b,27`
`jr nz,stop`	`otir`
	`ld hl, bist_adr`
	`ld (hl), bist_ack+bist_err`
	`halt`
	`nop`
	`nop`
`;worked: passed ;???? bjp`	`;worked: passed ;???? bjp`
`worked: push bc`	`worked: ld hl,match_msg`
`ld bc,(pass)`	`ld b,33`
`ld (message_addr),bc`	`otir`
`ld bc,(pass+2)`	`ld hl,pass_msg`
`ld (message_addr+2),bc`	`ld b,45`
`ld bc,(pass+4)`	`otir`
`ld (message_addr+4),bc`	`ld hl, bist_adr`
`pop bc`	`ld (hl), bist_ack`



`stop: halt`	`stop: halt`
`nop`	`nop`
`nop`	`nop`
`nop`	`nop`
`;`
	`int_start: push hl`
	`push bc`
	`push af ; bj -- this stuff gronks f as well`
	`ld hl, int_msg`
	`ld b, 1`
	`ld c, out_port`
	`otir`
	`pop af`
	`pop bc`
	`pop hl`
	`reti`

`;subroutine 1, must load a with #7f`	`;subroutine 1, must load a with #7f`
`;`	`;`
`sub1: ld a,data_7f`	`sub1: ld a,data_7f`
`ret`	`ret`
`;`	`;`
Line 6213...	Line 6250...
`ld a,1`	`ld a,1`
`ret`	`ret`
`;`	`;`
`; data`	`; data`
`;`	`;`

	`fail_msg: db cr,lf,'instruction test failed',cr,lf`
	`match_msg: db lf,'0123456 12345 12345 54321 54321',lf`
	`pass_msg: db 'If above lines match instruction test passed',lf`
	`int_msg: db bell`
	`;message_addr: equ #be58`

`var1: db data_ff`	`var1: db data_ff`
`var2: db data_55`	`var2: db data_55`
`var3: db data_80`	`var3: db data_80`
`var4: db data_aa`	`var4: db data_aa`
`var5: db data_7f`	`var5: db data_7f`
Line 6250...	Line 6294...
`org #7100`	`org #7100`
`stack: ds 128`	`stack: ds 128`
`stack_end: equ $`	`stack_end: equ $`
`;`	`;`
`end start`	`end start`
	`; only a single pointer in the interrupt table`
	`org #7200`
	`int_tbl: dw 0`
	`org #72fe`
	`int_ptr: dw int_start`

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[/] [wb_z80/] [trunk/] [asm/] [BJS80TST.ASM] - Diff between revs 26 and 30