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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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//// ////
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///////////////////////////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: z80_bist_logic.v,v 1.1 2004-05-13 14:57:35 bporcella Exp $
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// $Id: z80_bist_logic.v,v 1.2 2004-05-27 14:23:36 bporcella Exp $
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//
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//
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// $Date: 2004-05-13 14:57:35 $
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// $Date: 2004-05-27 14:23:36 $
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// $Revision: 1.1 $
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// $Revision: 1.2 $
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// $Author: bporcella $
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// $Author: bporcella $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2004/05/13 14:57:35 bporcella
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// testbed files
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//
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// Revision 1.1.1.1 2004/04/13 23:47:42 bporcella
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// Revision 1.1.1.1 2004/04/13 23:47:42 bporcella
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// import first files
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// import first files
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//
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//
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//
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//
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//
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//
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// Not much here. Just a very simple memory mapped register to
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// There are a few things here:
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// supply the required bist signals, and the commands necessary to
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// 1) A register to sequence the bist signals. A bist is run after rst, and the program
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// load the internal memory. Not that if thes bist is to be
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// indicates completion by setting bist_ack.
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// 2) A simple I/O device to aid in I/O instruction testing. The input device sequences
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// through a set of "interesting" data. The output device simply displays anything
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// written to it.
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// 3) A very simple interrupt generator. I guess this could be used as a clock in a real
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// system. Priority logic needs some work if that is to be done.
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//
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// Note that if thes bist is to be
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// actually synthesized a different method of loading the core SRAM
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// actually synthesized a different method of loading the core SRAM
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// (eq from external PROM) must be implemented.
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// (eq from external PROM) must be implemented.
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//
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//
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//-------1---------2---------3--------Module Name and Port List------7---------8---------9--------0
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//-------1---------2---------3--------Module Name and Port List------7---------8---------9--------0
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module z80_bist_logic( bist_err_o,
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module z80_bist_logic( bist_err_o,
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bist_ack_o,
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bist_ack_o,
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wb_dat_o ,
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wb_ack_o ,
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int_req_o ,
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wb_adr_i ,
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wb_adr_i ,
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wb_dat_i ,
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wb_dat_i ,
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wb_we_i ,
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wb_we_i ,
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wb_cyc_i ,
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wb_cyc_i ,
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wb_stb_i ,
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wb_stb_i ,
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wb_clk_i ,
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wb_clk_i ,
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wb_tga_i ,
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wb_tga_i ,
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int_req_i ,
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wb_rst_i );
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wb_rst_i );
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//-------1---------2---------3--------Output Ports---------6---------7---------8---------9--------0
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//-------1---------2---------3--------Output Ports---------6---------7---------8---------9--------0
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output bist_err_o;
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output bist_err_o;
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output bist_ack_o;
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output bist_ack_o;
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output [7:0] wb_dat_o;
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output wb_ack_o;
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output int_req_o;
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//-------1---------2---------3--------Input Ports----------6---------7---------8---------9--------0
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//-------1---------2---------3--------Input Ports----------6---------7---------8---------9--------0
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input [15:0] wb_adr_i;
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input [15:0] wb_adr_i;
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input wb_we_i;
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input wb_we_i;
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input wb_cyc_i;
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input wb_cyc_i;
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input wb_stb_i;
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input wb_stb_i;
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input [1:0] wb_tga_i;
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input [1:0] wb_tga_i;
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input wb_clk_i;
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input wb_clk_i;
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input wb_rst_i;
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input wb_rst_i;
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input [7:0] wb_dat_i;
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input [7:0] wb_dat_i;
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input int_req_i;
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//-------1---------2---------3--------Parameters-----------6---------7---------8---------9--------0
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//-------1---------2---------3--------Parameters-----------6---------7---------8---------9--------0
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//-------1---------2---------3--------Wires------5---------6---------7---------8---------9--------0
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//-------1---------2---------3--------Wires------5---------6---------7---------8---------9--------0
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//-------1---------2---------3--------Registers--5---------6---------7---------8---------9--------0
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//-------1---------2---------3--------Registers--5---------6---------7---------8---------9--------0
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reg [1:0] bist_reg;
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reg [2:0] bist_reg;
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integer i;
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integer i;
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reg wb_ack_o;
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reg [7:0] out_state;
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reg [9:0] int_count;
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reg int_req;
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wire int_ack;
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wire bist_int_en;
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//-------1---------2---------3--------Assignments----------6---------7---------8---------9--------0
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//-------1---------2---------3--------Assignments----------6---------7---------8---------9--------0
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assign bist_err_o = bist_reg[1];
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assign bist_err_o = bist_reg[1];
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assign bist_ack_o = bist_reg[0];
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assign bist_ack_o = bist_reg[0];
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assign bist_int_en = bist_reg[2];
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wire clk = wb_clk_i;
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wire rst = wb_rst_i;
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assign int_req_o = int_req_i | int_req & bist_int_en;
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//-------1---------2---------3--------State Machines-------6---------7---------8---------9--------0
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//-------1---------2---------3--------State Machines-------6---------7---------8---------9--------0
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// The following parameters are "known" to the instruction test program.
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// If you change them change the test program accorcingly.
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//
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parameter INT_OFFSET = 8'hfe; // int device provides offset to last entry of int table.
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parameter BIST_ADR = 16'hffff ; // address of bist register
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parameter MY_IO_ADR = 8'h20 ; // Map to " " for minor reasons related to "embedded test"
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parameter TAG_MEM = 2'b00,
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TAG_IO = 2'b01, // need to review general wb usage to undrstand how best to
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TAG_INT = 2'b10; // document this.
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// ----------------- a pretty simple I/O device ----------------------------------
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wire a2io = (wb_adr_i[7:0] == MY_IO_ADR) & wb_stb_i & wb_cyc_i & (wb_tga_i == TAG_IO);
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wire a2bist = (wb_adr_i == BIST_ADR) & wb_stb_i & wb_cyc_i & (wb_tga_i == TAG_MEM);
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assign int_ack = wb_stb_i & wb_cyc_i & (wb_tga_i == TAG_INT);
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always @(posedge clk or posedge rst)
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begin
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if (wb_rst_i ) wb_ack_o <= 1'b0;
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else if((a2io | a2bist | int_ack) & !wb_ack_o) wb_ack_o <= 1'b1;
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else wb_ack_o <= 1'b0;
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end
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// the "output" device - output simply displays the data written --
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always @(posedge clk or posedge rst)
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if (a2io & wb_we_i & wb_ack_o) $write("%s",wb_dat_i);
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// the "input" device --------------------------------------------------
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//
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// input cycles through
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// various interesting data patterens as used by the instruction test
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// namely 7f 55 80 0 ff aa
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assign wb_dat_o = int_ack ? INT_OFFSET : out_state;
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always @(posedge clk or posedge rst)
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begin
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if (wb_rst_i) out_state <= 8'h7f;
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else if (a2io & !wb_we_i & wb_ack_o)
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case (out_state)
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8'h7f: out_state <= 8'h55 ;
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8'h55: out_state <= 8'h80 ;
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8'h80: out_state <= 8'h00 ;
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8'h00: out_state <= 8'hff ;
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8'hff: out_state <= 8'haa ;
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8'haa: out_state <= 8'h7f ;
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default: out_state <= 8'h7f ;
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endcase
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end
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//----- memory mapped register ----------- for bist control
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// my address is selected as memory mapped to top of SDRAM.
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// my address is selected as memory mapped to top of SDRAM.
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// any system implementation may choose to modify this.
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// any system implementation may choose to modify this.
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wire wb_wr = wb_cyc_i & wb_stb_i & wb_we_i;
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wire wb_wr = wb_cyc_i & wb_stb_i & wb_we_i;
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wire my_adr = (wb_tga_i == 2'b00) & ( wb_adr_i == 16'h7fff);
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wire my_adr = (wb_tga_i == 2'b00) & ( wb_adr_i == BIST_ADR);
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always @(posedge wb_clk_i or wb_rst_i)
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always @(posedge wb_clk_i or wb_rst_i)
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if (wb_rst_i) bist_reg <= 2'b0;
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if (wb_rst_i) bist_reg <= 3'b0;
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else if (my_adr & wb_wr ) bist_reg <= wb_dat_i[1:0];
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else if (my_adr & wb_wr & wb_ack_o) bist_reg <= wb_dat_i[2:0];
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initial
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initial
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begin
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begin
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$readmemh( "readmem.txt", z80_testbed.i_z80_core_top.i_generic_spram.mem );
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$display("BL messages from Bist logic TB messages from test bench - others from test" );
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$display("BL dump a few memory locations to be sure initialization is sane") ;
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$readmemh( "readmem.txt", z80_testbed.i_z80_core_top.i_z80_sram.mem );
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// be sure at least some of the data got properly loaded.
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// be sure at least some of the data got properly loaded.
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for (i=0; i<10; i=i+1)
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for (i=0; i<10; i=i+1)
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$display( "mem [%0d] = %h", i, z80_testbed.i_z80_core_top.i_generic_spram.mem[i]);
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$display( "BL mem [%0d] = %h", i, z80_testbed.i_z80_core_top.i_z80_sram.mem[i]);
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end
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end
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//--------------------- the interrupt device ------------------------------
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always @(posedge wb_clk_i or wb_rst_i)
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if (wb_rst_i) int_count <=10'h0;
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else int_count <= int_count + 10'h1;
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always @(posedge wb_clk_i or wb_rst_i)
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if (wb_rst_i) int_req <= 1'b0;
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else if (int_count==10'h3ff) int_req <= 1'b1;
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else if ( int_ack ) int_req <= 1'b0;
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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