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Line 35... |
//// POSSIBILITY OF SUCH DAMAGE.
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//// POSSIBILITY OF SUCH DAMAGE.
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////
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////
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///////////////////////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: z80_core_top.v,v 1.4 2004-05-18 22:31:21 bporcella Exp $
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// $Id: z80_core_top.v,v 1.5 2004-05-21 02:51:25 bporcella Exp $
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//
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//
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// $Date: 2004-05-18 22:31:21 $
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// $Date: 2004-05-21 02:51:25 $
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// $Revision: 1.4 $
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// $Revision: 1.5 $
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// $Author: bporcella $
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// $Author: bporcella $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2004/05/18 22:31:21 bporcella
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// instruction test getting to final stages
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//
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// Revision 1.3 2004/05/13 14:58:53 bporcella
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// Revision 1.3 2004/05/13 14:58:53 bporcella
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// testbed built and verification in progress
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// testbed built and verification in progress
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//
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//
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// Revision 1.2 2004/04/27 21:38:22 bporcella
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// Revision 1.2 2004/04/27 21:38:22 bporcella
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// test lint on core
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// test lint on core
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| Line 122... |
Line 125... |
wire [15:0] sp;
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wire [15:0] sp;
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wire [7:0] ar, fr, br, cr, dr, er, hr, lr, intr;
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wire [7:0] ar, fr, br, cr, dr, er, hr, lr, intr;
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wire [15:0] ixr, iyr;
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wire [15:0] ixr, iyr;
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wire [7:0] wb_dat_i, wb_dat_o, sdram_do, cfg_do;
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wire [7:0] wb_dat_i, wb_dat_o, sdram_do, cfg_do;
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wire [15:0] add16; // ir2 execution engine output for sp updates
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wire [15:0] add16; // ir2 execution engine output for sp updates
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wire [15:0] adr_alu; // address alu to inst to update hl and de on block moves
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wire [7:0] alu8_out, sh_alu, bit_alu;
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wire [7:0] alu8_out, sh_alu, bit_alu;
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| Line 146... |
Line 150... |
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z80_memstate2 i_z80_memstate2(
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z80_memstate2 i_z80_memstate2(
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.wb_adr_o(wb_adr_o), .wb_we_o(wb_we_o), .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_tga_o(wb_tga_o), .wb_dat_o(wb_dat_o),
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.wb_adr_o(wb_adr_o), .wb_we_o(wb_we_o), .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_tga_o(wb_tga_o), .wb_dat_o(wb_dat_o),
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.exec_ir2(exec_ir2), .ir1(ir1), .ir2(ir2), .ir1dd(ir1dd), .ir1fd(ir1fd), .ir2dd(ir2dd), .ir2fd(ir2fd), .nn(nn), .sp(sp),
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.exec_ir2(exec_ir2),
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.exec_decbc(exec_decbc), .exec_decb(exec_decb),
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.ir1(ir1), .ir2(ir2), .ir1dd(ir1dd), .ir1fd(ir1fd), .ir2dd(ir2dd), .ir2fd(ir2fd), .nn(nn), .sp(sp),
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.upd_ar(upd_ar), .upd_br(upd_br), .upd_cr(upd_cr), .upd_dr(upd_dr), .upd_er(upd_er), .upd_hr(upd_hr), .upd_lr(upd_lr),.upd_fr(upd_fr),
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.upd_ar(upd_ar), .upd_br(upd_br), .upd_cr(upd_cr), .upd_dr(upd_dr), .upd_er(upd_er), .upd_hr(upd_hr), .upd_lr(upd_lr),.upd_fr(upd_fr),
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.beq0(br_eq0), .ceq0(cr_eq0),
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.beq0(br_eq0), .ceq0(cr_eq0),
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.ar(ar), .fr(fr), .br(br), .cr(cr), .dr(dr), .er(er), .hr(hr), .lr(lr),
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.ar(ar), .fr(fr), .br(br), .cr(cr), .dr(dr), .er(er), .hr(hr), .lr(lr),
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.ixr(ixr), .iyr(iyr),
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.ixr(ixr), .iyr(iyr),
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.wb_dat_i(cfg_do), .wb_ack_i(cfg_ack_o),
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.wb_dat_i(cfg_do), .wb_ack_i(cfg_ack_o),
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.int_req_i(int_req_i),
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.int_req_i(int_req_i),
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.add16(add16),
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.add16(add16),
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.alu8_out(alu8_out),
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.alu8_out(alu8_out),
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.adr_alu(adr_alu),
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.blk_mv_upd_hl(blk_mv_upd_hl),
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.blk_mv_upd_de(blk_mv_upd_de),
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.sh_alu(sh_alu),
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.sh_alu(sh_alu),
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.bit_alu(bit_alu),
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.bit_alu(bit_alu),
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.wb_clk_i(wb_clk_i),
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.wb_clk_i(wb_clk_i),
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.rst_i(wb_rst_i) // keep this generic - may turn out to be different from wb_rst
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.rst_i(wb_rst_i) // keep this generic - may turn out to be different from wb_rst
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);
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);
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| Line 168... |
Line 177... |
.br_eq0(br_eq0),
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.br_eq0(br_eq0),
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.cr_eq0(cr_eq0),
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.cr_eq0(cr_eq0),
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.upd_ar(upd_ar), .upd_br(upd_br), .upd_cr(upd_cr), .upd_dr(upd_dr), .upd_er(upd_er), .upd_hr(upd_hr), .upd_lr(upd_lr),.upd_fr(upd_fr),
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.upd_ar(upd_ar), .upd_br(upd_br), .upd_cr(upd_cr), .upd_dr(upd_dr), .upd_er(upd_er), .upd_hr(upd_hr), .upd_lr(upd_lr),.upd_fr(upd_fr),
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.ar(ar), .fr(fr), .br(br), .cr(cr), .dr(dr), .er(er), .hr(hr), .lr(lr), .intr(intr),
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.ar(ar), .fr(fr), .br(br), .cr(cr), .dr(dr), .er(er), .hr(hr), .lr(lr), .intr(intr),
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.ixr(ixr), .iyr(iyr), .add16(add16), .alu8_out(alu8_out),
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.ixr(ixr), .iyr(iyr), .add16(add16), .alu8_out(alu8_out),
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.adr_alu(adr_alu),
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.blk_mv_upd_hl(blk_mv_upd_hl),
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.blk_mv_upd_de(blk_mv_upd_de),
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.sh_alu(sh_alu),
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.sh_alu(sh_alu),
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.bit_alu(bit_alu),
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.bit_alu(bit_alu),
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.exec_ir2(exec_ir2),
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.exec_ir2(exec_ir2),
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.exec_decbc(exec_decbc), .exec_decb(exec_decb),
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.exec_decbc(exec_decbc), .exec_decb(exec_decb),
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.ir2(ir2),
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.ir2(ir2),
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