| Line 69... |
Line 69... |
// the intention is that even if the synthesizer is pretty primitive -- reasonably fast hardware
|
// the intention is that even if the synthesizer is pretty primitive -- reasonably fast hardware
|
// will be produced.
|
// will be produced.
|
//
|
//
|
//-------1---------2---------3--------CVS Log -----------------------7---------8---------9--------0
|
//-------1---------2---------3--------CVS Log -----------------------7---------8---------9--------0
|
//
|
//
|
// $Id: z80_inst_exec.v,v 1.1 2004-04-27 21:27:13 bporcella Exp $
|
// $Id: z80_inst_exec.v,v 1.2 2004-05-13 14:58:53 bporcella Exp $
|
//
|
//
|
// $Date: 2004-04-27 21:27:13 $
|
// $Date: 2004-05-13 14:58:53 $
|
// $Revision: 1.1 $
|
// $Revision: 1.2 $
|
// $Author: bporcella $
|
// $Author: bporcella $
|
// $Locker: $
|
// $Locker: $
|
// $State: Exp $
|
// $State: Exp $
|
//
|
//
|
// Change History:
|
// Change History:
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.1 2004/04/27 21:27:13 bporcella
|
|
// first core build
|
|
//
|
// Revision 1.4 2004/04/19 19:13:27 bporcella
|
// Revision 1.4 2004/04/19 19:13:27 bporcella
|
// real lint problems pretty much fixed -- need another look - but need to get on to other things first
|
// real lint problems pretty much fixed -- need another look - but need to get on to other things first
|
//
|
//
|
// Revision 1.3 2004/04/19 05:09:11 bporcella
|
// Revision 1.3 2004/04/19 05:09:11 bporcella
|
// fixed some lint problems --
|
// fixed some lint problems --
|
| Line 97... |
Line 100... |
//
|
//
|
//-------1---------2---------3--------Module Name and Port List------7---------8---------9--------0
|
//-------1---------2---------3--------Module Name and Port List------7---------8---------9--------0
|
module z80_inst_exec( br_eq0,
|
module z80_inst_exec( br_eq0,
|
cr_eq0,
|
cr_eq0,
|
upd_ar, upd_br, upd_cr, upd_dr, upd_er, upd_hr, upd_lr,upd_fr,
|
upd_ar, upd_br, upd_cr, upd_dr, upd_er, upd_hr, upd_lr,upd_fr,
|
ar, fr, br, cr, dr, er, hr, lr,
|
ar, fr, br, cr, dr, er, hr, lr, intr,
|
ixr, iyr, add16,
|
ixr, iyr, add16,
|
exec_ir2,
|
exec_ir2,
|
exec_decbc, exec_decb,
|
exec_decbc, exec_decb,
|
ir2,
|
ir2,
|
clk,
|
clk,
|
rst,
|
rst,
|
nn, sp,
|
nn, sp,
|
dd_grp,
|
ir2dd,
|
fd_grp
|
ir2fd
|
);
|
);
|
|
|
//-------1---------2---------3--------Output Ports---------6---------7---------8---------9--------0
|
//-------1---------2---------3--------Output Ports---------6---------7---------8---------9--------0
|
output br_eq0;
|
output br_eq0;
|
output cr_eq0;
|
output cr_eq0;
|
output upd_ar, upd_br, upd_cr, upd_dr, upd_er, upd_hr, upd_lr,upd_fr;
|
output upd_ar, upd_br, upd_cr, upd_dr, upd_er, upd_hr, upd_lr,upd_fr;
|
output [7:0] ar, fr, br, cr, dr, er, hr, lr;
|
output [7:0] ar, fr, br, cr, dr, er, hr, lr, intr;
|
output [15:0] ixr, iyr;
|
output [15:0] ixr, iyr;
|
output [15:0] add16;
|
output [15:0] add16;
|
//-------1---------2---------3--------Input Ports----------6---------7---------8---------9--------0
|
//-------1---------2---------3--------Input Ports----------6---------7---------8---------9--------0
|
input exec_ir2;
|
input exec_ir2;
|
input exec_decbc; // in general this needs to happen at different time from exec
|
input exec_decbc; // in general this needs to happen at different time from exec
|
input exec_decb; // in general - we don't have the EB instruction (yet) when this hits
|
input exec_decb; // in general - we don't have the EB instruction (yet) when this hits
|
input [9:0] ir2;
|
input [9:0] ir2;
|
input clk;
|
input clk;
|
input rst;
|
input rst;
|
input [15:0] nn, sp;
|
input [15:0] nn, sp;
|
input dd_grp; // this must be ir2
|
input ir2dd; // this must be ir2
|
input fd_grp;
|
input ir2fd;
|
|
|
//-------1---------2---------3--------Parameters-----------6---------7---------8---------9--------0
|
//-------1---------2---------3--------Parameters-----------6---------7---------8---------9--------0
|
`include "opcodes.v"
|
`include "opcodes.v"
|
|
|
//-------1---------2---------3--------Wires----------------6---------7---------8---------9--------0
|
//-------1---------2---------3--------Wires----------------6---------7---------8---------9--------0
|
| Line 201... |
Line 204... |
wire upd_fr_alu8 ;
|
wire upd_fr_alu8 ;
|
wire upd_fr_add16 ;
|
wire upd_fr_add16 ;
|
wire upd_fr_edadd16 ;
|
wire upd_fr_edadd16 ;
|
wire upd_fr_sh ;
|
wire upd_fr_sh ;
|
wire upd_fr_cbsh ;
|
wire upd_fr_cbsh ;
|
wire eb_blk_mv ;
|
//wire eb_blk_mv ;
|
wire ed_blk_cp ;
|
wire ed_blk_cp ;
|
wire c_8in0 ;
|
wire c_8in0 ;
|
|
|
//-------1---------2---------3--------Registers------------6---------7---------8---------9--------0
|
//-------1---------2---------3--------Registers------------6---------7---------8---------9--------0
|
|
|
| Line 218... |
Line 221... |
// specifically, it is assumed that a memory operation is to be implemented (ix + d)
|
// specifically, it is assumed that a memory operation is to be implemented (ix + d)
|
// , In fact the
|
// , In fact the
|
// pipeline is such that we can make a fetch for free - so we will do that..... the
|
// pipeline is such that we can make a fetch for free - so we will do that..... the
|
// prefix flags should not be set here -- all we will know on execution is that it is a
|
// prefix flags should not be set here -- all we will know on execution is that it is a
|
// cb instruction. ---- src is always nn
|
// cb instruction. ---- src is always nn
|
assign src_hr = dd_grp ? ixr[15:8] :
|
assign src_hr = ir2dd ? ixr[15:8] :
|
fd_grp ? iyr[15:8] :
|
ir2fd ? iyr[15:8] :
|
hr ;
|
hr ;
|
|
|
assign src_lr = dd_grp ? ixr[7:0] :
|
assign src_lr = ir2dd ? ixr[7:0] :
|
fd_grp ? iyr[7:0] :
|
ir2fd ? iyr[7:0] :
|
lr ;
|
lr ;
|
|
|
assign src_dblhr = dd_grp ? ixr : // ed grp instructions (ADC HL ; SBC HL are not affected -
|
assign src_dblhr = ir2dd ? ixr : // ed grp instructions (ADC HL ; SBC HL are not affected -
|
fd_grp ? iyr : // instruction assembler assures this - ed_grp has no prefix
|
ir2fd ? iyr : // instruction assembler assures this - ed_grp has no prefix
|
{hr, lr} ;
|
{hr, lr} ;
|
// ddcb_grp not defined - src_cb_r20 not used. Why these lines? 4/17/2004
|
// ddcb_grp not defined - src_cb_r20 not used. Why these lines? 4/17/2004
|
//assign src_cb_r20 = (ddcb_grp | fdcb_grp) ? nn[7:0] :
|
//assign src_cb_r20 = (ddcb_grp | fdcb_grp) ? nn[7:0] :
|
// cb_grp ? src_pqr20 :
|
// cb_grp ? src_pqr20 :
|
// ar ;
|
// ar ;
|
| Line 259... |
Line 262... |
assign src_dbl = {16{ir2[5:4]==2'b00}} & {br, cr} |
|
assign src_dbl = {16{ir2[5:4]==2'b00}} & {br, cr} |
|
{16{ir2[5:4]==2'b01}} & {dr, er} |
|
{16{ir2[5:4]==2'b01}} & {dr, er} |
|
{16{ir2[5:4]==2'b10}} & src_dblhr | // HL, ixr, iyr
|
{16{ir2[5:4]==2'b10}} & src_dblhr | // HL, ixr, iyr
|
{16{ir2[5:4]==2'b11}} & sp ;
|
{16{ir2[5:4]==2'b11}} & sp ;
|
|
|
assign sh_src = ir2[8] & dd_grp ? nn[15:8] :
|
assign sh_src = ir2[8] & ir2dd ? nn[15:8] :
|
ir2[8] & fd_grp ? nn[15:8] :
|
ir2[8] & ir2fd ? nn[15:8] :
|
ir2 ? src_pqr20 :
|
ir2[8] ? src_pqr20 :
|
ar ;
|
ar ;
|
// I wonder how well the synthesizer can reduce this??? - It is probably worth spending
|
// I wonder how well the synthesizer can reduce this??? - It is probably worth spending
|
// some time during physical design to see if a more low level description would help --
|
// some time during physical design to see if a more low level description would help --
|
// there is somebody out there who knows - and there is probably a good low level description.
|
// there is somebody out there who knows - and there is probably a good low level description.
|
//
|
//
|
| Line 309... |
Line 312... |
// sf zf f5f hf
|
// sf zf f5f hf
|
assign alu8_fr ={alu8_out[7], ~|alu8_out, alu8_out[5], alu8_hcry,
|
assign alu8_fr ={alu8_out[7], ~|alu8_out, alu8_out[5], alu8_hcry,
|
// f3f fpv fn fc
|
// f3f fpv fn fc
|
alu8_out[3], alu8_out[7], alu8_nf, c_8out7 };
|
alu8_out[3], alu8_out[7], alu8_nf, c_8out7 };
|
|
|
//assign alu8_pvf = (ir2[7:3]==5'b10100 | ir2[7:3]==5'b10101 | ir2[7:3]==5'b10110) ?
|
//assign alu8_pvf = (ir2[9:3]==5'b10100 | ir2[9:3]==5'b10101 | ir2[7:3]==5'b10110) ?
|
// ~^alu8_out : // even parity
|
// ~^alu8_out : // even parity
|
// (src_aor_cnst[7]==src_pqri[7]) & (src_aor_cnst[7]!=alu8_out[7]) ; // ofl
|
// (src_aor_cnst[7]==src_pqri[7]) & (src_aor_cnst[7]!=alu8_out[7]) ; // ofl
|
|
|
assign alu8_nf = (ir2[7:3]==5'b10010) |
|
assign alu8_nf = (ir2[7:3]==5'b10010) |
|
(ir2[7:3]==5'b10011) |
|
(ir2[7:3]==5'b10011) |
|
| Line 333... |
Line 336... |
// 1 1 8 8 1
|
// 1 1 8 8 1
|
assign {alu8_cry, alu8_hcry, alu8_out, src_pqri, c_8in0 }=
|
assign {alu8_cry, alu8_hcry, alu8_out, src_pqri, c_8in0 }=
|
|
|
ed_blk_cp ? {c_8out7,c_8out3, add_8bit, ~src_pqr20, 1'h1} : //CPI CPIR CPD CPDR
|
ed_blk_cp ? {c_8out7,c_8out3, add_8bit, ~src_pqr20, 1'h1} : //CPI CPIR CPD CPDR
|
|
|
{19{ir2[7:3]==5'b10000}} & ({c_8out7,c_8out3, add_8bit, src_pqr20, 1'b0} ) |// a+src
|
{19{ir2[7] & ir2[5:3]==3'b000}} & ({c_8out7,c_8out3, add_8bit, src_pqr20, 1'b0} ) |// a+src
|
{19{ir2[7:3]==5'b10001}} & ({c_8out7,c_8out3, add_8bit, src_pqr20, cf} ) |// a+src+cf
|
{19{ir2[7] & ir2[5:3]==5'b001}} & ({c_8out7,c_8out3, add_8bit, src_pqr20, cf} ) |// a+src+cf
|
{19{ir2[7:3]==5'b10010}} & ({c_8out7,c_8out3, add_8bit, ~src_pqr20, 1'h1} ) |// a-src
|
{19{ir2[7] & ir2[5:3]==5'b010}} & ({c_8out7,c_8out3, add_8bit, ~src_pqr20, 1'h1} ) |// a-src
|
{19{ir2[7:3]==5'b10011}} & ({c_8out7,c_8out3, add_8bit, ~src_pqr20, ~cf } ) |// a-src-cf
|
{19{ir2[7] & ir2[5:3]==5'b011}} & ({c_8out7,c_8out3, add_8bit, ~src_pqr20, ~cf } ) |// a-src-cf
|
{19{ir2[7:3]==5'b10100}} & ({1'b0 ,1'b1 , ar & src_pqr20, src_pqr20, 1'b0} ) |// a&src
|
{19{ir2[7] & ir2[5:3]==5'b100}} & ({1'b0 ,1'b1 , ar & src_pqr20, src_pqr20, 1'b0} )|// a&src
|
{19{ir2[7:3]==5'b10101}} & ({1'b0 ,1'b0 , ar ^ src_pqr20, src_pqr20, 1'b0} ) |// a^src
|
{19{ir2[7] & ir2[5:3]==5'b101}} & ({1'b0 ,1'b0 , ar ^ src_pqr20, src_pqr20, 1'b0} )|// a^src
|
{19{ir2[7:3]==5'b10110}} & ({1'b0 ,1'b0 , ar | src_pqr20, src_pqr20, 1'b0} ) |// a|src
|
{19{ir2[7] & ir2[5:3]==5'b110}} & ({1'b0 ,1'b0 , ar | src_pqr20, src_pqr20, 1'b0} )|// a|src
|
{19{ir2[7:3]==5'b10111}} & ({c_8out7,c_8out3, add_8bit, src_pqr20, 1'h1}) |// a-src
|
{19{ir2[7] & ir2[5:3]==5'b111}} & ({c_8out7,c_8out3, add_8bit, ~src_pqr20, 1'h1}) |// a-src
|
{19{(ir2[7:6]==2'b00)& ~ir2[0] }}& ({ cf,c_8out3, add_8bit, src_pqr53, 1'h1}) |// inc_r main
|
{19{(ir2[7:6]==2'b00)& ~ir2[0] }}& ({ cf,c_8out3, add_8bit, src_pqr53, 1'h1}) |// inc_r main
|
{19{(ir2[7:6]==2'b00)& ir2[0] }}& ({ cf,c_8out3, add_8bit, src_pqr53, 1'h0}) |// dec_r
|
{19{(ir2[7:6]==2'b00)& ir2[0] }}& ({ cf,c_8out3, add_8bit, src_pqr53, 1'h0}) |// dec_r
|
{19{(ir2[7:6]==2'b01) }}& ({c_8out7,c_8out3, add_8bit, ~ar, 1'h1}) ;// ed44 -a
|
{19{(ir2[7:6]==2'b01) }}& ({c_8out7,c_8out3, add_8bit, ~ar, 1'h1}) ;// ed44 -a
|
|
|
|
|
| Line 377... |
Line 380... |
// shift insructions. Think of these as 8 shift types:
|
// shift insructions. Think of these as 8 shift types:
|
// RLC RL RRC RR SLA SLL SRA SRL The SLL types appear to be undocumented -- but possibly used
|
// RLC RL RRC RR SLA SLL SRA SRL The SLL types appear to be undocumented -- but possibly used
|
// in assembly code as they appear to have some utility - and by all accounts operate reliably.
|
// in assembly code as they appear to have some utility - and by all accounts operate reliably.
|
// The first four are implemented in a single byte inaruction . (A <= sh_op A )
|
// The first four are implemented in a single byte inaruction . (A <= sh_op A )
|
// All 8 are implemented in the CB group with all registers as potential sources (and dests).
|
// All 8 are implemented in the CB group with all registers as potential sources (and dests).
|
// if dd_grp or fd_grp is prefix..... source is always the memory. This is undocumented - but
|
// if ir2dd or ir2fd is prefix..... source is always the memory. This is undocumented - but
|
// may be a useful hint for simplyfing the total machine. Destination registers
|
// may be a useful hint for simplyfing the total machine. Destination registers
|
// (if any) get a copy of the updated memory location (This is also true of the bit set and
|
// (if any) get a copy of the updated memory location (This is also true of the bit set and
|
// clear instructions in the cb_grp.
|
// clear instructions in the cb_grp.
|
|
|
assign {sh_cry, sh_alu} = {9{ir2[5:3]==3'b000}} & {sh_src, sh_src[7] } | //RLC
|
assign {sh_cry, sh_alu} = {9{ir2[5:3]==3'b000}} & {sh_src, sh_src[7] } | //RLC
|
| Line 535... |
Line 538... |
always @(posedge clk)
|
always @(posedge clk)
|
begin
|
begin
|
if (upd_a_alu8 & exec_ir2) ar <= alu8_out;
|
if (upd_a_alu8 & exec_ir2) ar <= alu8_out;
|
if (up_a_sh_alu & exec_ir2) ar <= sh_alu;
|
if (up_a_sh_alu & exec_ir2) ar <= sh_alu;
|
if (up_a_src_pqr & exec_ir2) ar <= src_pqr20;
|
if (up_a_src_pqr & exec_ir2) ar <= src_pqr20;
|
if (up_a_n & exec_ir2) ar <= nn[7:0];
|
if (up_a_n & exec_ir2) ar <= nn[15:8]; // changed for LD A N
|
if (ir2 == EXsAF_AFp & exec_ir2) ar <= ap;
|
if (ir2 == EXsAF_AFp & exec_ir2) ar <= ap;
|
if (ir2 == EXX & exec_ir2) ar <= ap;
|
if (ir2 == EXX & exec_ir2) ar <= ap;
|
if (ir2 == DAA & exec_ir2) ar <= daa_alu;
|
if (ir2 == DAA & exec_ir2) ar <= daa_alu;
|
if (ir2 == CPL & exec_ir2) ar <= ~ar;
|
if (ir2 == CPL & exec_ir2) ar <= ~ar;
|
if (ir2 == POPsAF & exec_ir2) ar <= nn[15:8];
|
if (ir2 == POPsAF & exec_ir2) ar <= nn[15:8];
|
| Line 618... |
Line 621... |
if ( up_b_src_pqr & exec_ir2) br <= src_pqr20;
|
if ( up_b_src_pqr & exec_ir2) br <= src_pqr20;
|
if ( up_b_add16 & exec_ir2) br <= add16[15:8];
|
if ( up_b_add16 & exec_ir2) br <= add16[15:8];
|
if ( LDsBC_NN == ir2 & exec_ir2) br <= nn[15:8];
|
if ( LDsBC_NN == ir2 & exec_ir2) br <= nn[15:8];
|
if ( POPsBC == ir2 & exec_ir2) br <= nn[15:8];
|
if ( POPsBC == ir2 & exec_ir2) br <= nn[15:8];
|
if ( EXX == ir2 & exec_ir2) br <= bp;
|
if ( EXX == ir2 & exec_ir2) br <= bp;
|
if ( LDsB_N == ir2 & exec_ir2) br <= nn[7:0];
|
if ( LDsB_N == ir2 & exec_ir2) br <= nn[15:8];
|
if (ir2[2:0] == REG8_B &
|
if (ir2[2:0] == REG8_B &
|
bit_alu_act & exec_ir2) br <= bit_alu;
|
bit_alu_act & exec_ir2) br <= bit_alu;
|
if (ir2[2:0] == REG8_B &
|
if (ir2[2:0] == REG8_B &
|
sh_alu_act & exec_ir2) br <= sh_alu;
|
sh_alu_act & exec_ir2) br <= sh_alu;
|
if ( DJNZs$t2 == ir2 & exec_ir2) br <= br + 8'hff; // use seperate adder here as no flags
|
if ( DJNZs$t2 == ir2 & exec_ir2) br <= br + 8'hff; // use seperate adder here as no flags
|
// change -- we need br==0. for now
|
// change -- we need br==0. for now
|
// use |br. If we need more speed add
|
// use |br. If we need more speed add
|
// a ff.
|
// a ff.
|
if (exec_decb | exec_decbc) br <= decb_alu;
|
if (exec_decb | exec_decbc) br <= decb_alu;
|
if ( (ED_INsREG_6C7 == {ir2[7:6],ir2[2:0]}) & (ir2[5:3] == REG8_B) & exec_ir2 )
|
if ( (ED_INsREG_6C7 == {ir2[9:6],ir2[2:0]}) & (ir2[5:3] == REG8_B) & exec_ir2 )
|
br <= nn[7:0];
|
br <= nn[7:0];
|
end
|
end
|
|
|
|
|
// update cr
|
// update cr
|
| Line 673... |
Line 676... |
if ( up_c_src_pqr & exec_ir2) cr <= src_pqr20;
|
if ( up_c_src_pqr & exec_ir2) cr <= src_pqr20;
|
if ( up_c_add16 & exec_ir2) cr <= add16[7:0];
|
if ( up_c_add16 & exec_ir2) cr <= add16[7:0];
|
if ( LDsBC_NN == ir2 & exec_ir2) cr <= nn[7:0];
|
if ( LDsBC_NN == ir2 & exec_ir2) cr <= nn[7:0];
|
if ( POPsBC == ir2 & exec_ir2) cr <= nn[7:0];
|
if ( POPsBC == ir2 & exec_ir2) cr <= nn[7:0];
|
if ( EXX == ir2 & exec_ir2) cr <= cp;
|
if ( EXX == ir2 & exec_ir2) cr <= cp;
|
if ( LDsC_N == ir2 & exec_ir2) cr <= nn[7:0];
|
if ( LDsC_N == ir2 & exec_ir2) cr <= nn[15:8];
|
if (ir2[2:0] == REG8_C &
|
if (ir2[2:0] == REG8_C &
|
bit_alu_act & exec_ir2) cr <= bit_alu;
|
bit_alu_act & exec_ir2) cr <= bit_alu;
|
if (ir2[2:0] == REG8_C &
|
if (ir2[2:0] == REG8_C &
|
sh_alu_act & exec_ir2) cr <= sh_alu;
|
sh_alu_act & exec_ir2) cr <= sh_alu;
|
if ( exec_decbc) cr <= decc_alu;
|
if ( exec_decbc) cr <= decc_alu;
|
| Line 732... |
Line 735... |
if ( up_d_add16 & exec_ir2) dr <= add16[15:8];
|
if ( up_d_add16 & exec_ir2) dr <= add16[15:8];
|
if ( LDsDE_NN == ir2 & exec_ir2) dr <= nn[15:8];
|
if ( LDsDE_NN == ir2 & exec_ir2) dr <= nn[15:8];
|
if ( POPsDE == ir2 & exec_ir2) dr <= nn[15:8];
|
if ( POPsDE == ir2 & exec_ir2) dr <= nn[15:8];
|
if ( EXX == ir2 & exec_ir2) dr <= dp;
|
if ( EXX == ir2 & exec_ir2) dr <= dp;
|
if ( EXsDE_HL == ir2 & exec_ir2) dr <= hr;
|
if ( EXsDE_HL == ir2 & exec_ir2) dr <= hr;
|
if ( LDsD_N == ir2 & exec_ir2) dr <= nn[7:0];
|
if ( LDsD_N == ir2 & exec_ir2) dr <= nn[15:8];
|
if (ir2[2:0] == REG8_D &
|
if (ir2[2:0] == REG8_D &
|
bit_alu_act & exec_ir2) dr <= bit_alu;
|
bit_alu_act & exec_ir2) dr <= bit_alu;
|
if (ir2[2:0] == REG8_D &
|
if (ir2[2:0] == REG8_D &
|
sh_alu_act & exec_ir2) dr <= sh_alu;
|
sh_alu_act & exec_ir2) dr <= sh_alu;
|
if ((ED_INsREG_6C7 == {ir2[9:6],ir2[2:0]})
|
if ((ED_INsREG_6C7 == {ir2[9:6],ir2[2:0]})
|
| Line 792... |
Line 795... |
if ( up_e_add16 & exec_ir2) er <= add16[7:0];
|
if ( up_e_add16 & exec_ir2) er <= add16[7:0];
|
if ( LDsDE_NN == ir2 & exec_ir2) er <= nn[7:0];
|
if ( LDsDE_NN == ir2 & exec_ir2) er <= nn[7:0];
|
if ( POPsDE == ir2 & exec_ir2) er <= nn[7:0];
|
if ( POPsDE == ir2 & exec_ir2) er <= nn[7:0];
|
if ( EXX == ir2 & exec_ir2) er <= ep;
|
if ( EXX == ir2 & exec_ir2) er <= ep;
|
if ( EXsDE_HL == ir2 & exec_ir2) er <= hr;
|
if ( EXsDE_HL == ir2 & exec_ir2) er <= hr;
|
if ( LDsE_N == ir2 & exec_ir2) er <= nn[7:0];
|
if ( LDsE_N == ir2 & exec_ir2) er <= nn[15:8];
|
if (ir2[2:0] == REG8_E &
|
if (ir2[2:0] == REG8_E &
|
bit_alu_act & exec_ir2) er <= bit_alu;
|
bit_alu_act & exec_ir2) er <= bit_alu;
|
if (ir2[2:0] == REG8_E &
|
if (ir2[2:0] == REG8_E &
|
sh_alu_act & exec_ir2) er <= sh_alu;
|
sh_alu_act & exec_ir2) er <= sh_alu;
|
if ((ED_INsREG_6C7 == {ir2[9:6],ir2[2:0]}) & (ir2[5:3] == REG8_E) & exec_ir2)
|
if ((ED_INsREG_6C7 == {ir2[9:6],ir2[2:0]}) & (ir2[5:3] == REG8_E) & exec_ir2)
|
| Line 848... |
Line 851... |
(ED_INsREG_6C7 == {ir2[9:6],ir2[2:0]}) & (ir2[5:3] == REG8_H);
|
(ED_INsREG_6C7 == {ir2[9:6],ir2[2:0]}) & (ir2[5:3] == REG8_H);
|
|
|
|
|
|
|
|
|
wire exec_hlir2 = exec_ir2 & !(dd_grp | fd_grp);
|
wire exec_hlir2 = exec_ir2 & !(ir2dd | ir2fd);
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
begin
|
begin
|
if ( upd_h_alu8 & exec_hlir2) hr <= alu8_out;
|
if ( upd_h_alu8 & exec_hlir2) hr <= alu8_out;
|
if ( upd_h_src_pqr & exec_hlir2) hr <= src_pqr20;
|
if ( upd_h_src_pqr & exec_hlir2) hr <= src_pqr20;
|
| Line 861... |
Line 864... |
if ( LDsHL_6NN7== ir2 & exec_hlir2) hr <= nn[15:8];
|
if ( LDsHL_6NN7== ir2 & exec_hlir2) hr <= nn[15:8];
|
if ( POPsHL == ir2 & exec_hlir2) hr <= nn[15:8];
|
if ( POPsHL == ir2 & exec_hlir2) hr <= nn[15:8];
|
if ( EXs6SP7_HL== ir2 & exec_hlir2) hr <= nn[15:8];
|
if ( EXs6SP7_HL== ir2 & exec_hlir2) hr <= nn[15:8];
|
if ( EXX == ir2 & exec_ir2) hr <= hp;
|
if ( EXX == ir2 & exec_ir2) hr <= hp;
|
if ( EXsDE_HL == ir2 & exec_ir2) hr <= dr;
|
if ( EXsDE_HL == ir2 & exec_ir2) hr <= dr;
|
if ( LDsH_N == ir2 & exec_hlir2) hr <= nn[7:0];
|
if ( LDsH_N == ir2 & exec_hlir2) hr <= nn[15:8];
|
if (ir2[2:0] == REG8_H &
|
if (ir2[2:0] == REG8_H &
|
bit_alu_act & exec_hlir2) hr <= bit_alu;
|
bit_alu_act & exec_hlir2) hr <= bit_alu;
|
if (ir2[2:0] == REG8_H &
|
if (ir2[2:0] == REG8_H &
|
sh_alu_act & exec_hlir2) hr <= sh_alu;
|
sh_alu_act & exec_hlir2) hr <= sh_alu;
|
if ((ED_INsREG_6C7 == {ir2[9:6],ir2[2:0]}) & (ir2[5:3] == REG8_H) & exec_ir2)
|
if ((ED_INsREG_6C7 == {ir2[9:6],ir2[2:0]}) & (ir2[5:3] == REG8_H) & exec_ir2)
|
| Line 921... |
Line 924... |
if ( LDsHL_6NN7== ir2 & exec_hlir2) lr <= nn[7:0];
|
if ( LDsHL_6NN7== ir2 & exec_hlir2) lr <= nn[7:0];
|
if ( POPsHL == ir2 & exec_hlir2) lr <= nn[7:0];
|
if ( POPsHL == ir2 & exec_hlir2) lr <= nn[7:0];
|
if ( EXs6SP7_HL== ir2 & exec_hlir2) lr <= nn[7:0];
|
if ( EXs6SP7_HL== ir2 & exec_hlir2) lr <= nn[7:0];
|
if ( EXX == ir2 & exec_ir2) lr <= lp;
|
if ( EXX == ir2 & exec_ir2) lr <= lp;
|
if ( EXsDE_HL == ir2 & exec_ir2) lr <= er;
|
if ( EXsDE_HL == ir2 & exec_ir2) lr <= er;
|
if ( LDsL_N == ir2 & exec_hlir2) lr <= nn[7:0];
|
if ( LDsL_N == ir2 & exec_hlir2) lr <= nn[15:8];
|
if (ir2[2:0] == REG8_L &
|
if (ir2[2:0] == REG8_L &
|
bit_alu_act & exec_hlir2) lr <= bit_alu;
|
bit_alu_act & exec_hlir2) lr <= bit_alu;
|
if (ir2[2:0] == REG8_L &
|
if (ir2[2:0] == REG8_L &
|
sh_alu_act & exec_hlir2) lr <= sh_alu;
|
sh_alu_act & exec_hlir2) lr <= sh_alu;
|
if ((ED_INsREG_6C7 == {ir2[9:6],ir2[2:0]}) & (ir2[5:3] == REG8_L) & exec_ir2)
|
if ((ED_INsREG_6C7 == {ir2[9:6],ir2[2:0]}) & (ir2[5:3] == REG8_L) & exec_ir2)
|
lr <= nn[7:0];
|
lr <= nn[7:0];
|
|
|
end
|
end
|
//------------------------ ixr ---------------------------------------------
|
//------------------------ ixr ---------------------------------------------
|
wire exec_ixir2 = exec_ir2 & dd_grp;
|
wire exec_ixir2 = exec_ir2 & ir2dd;
|
always @(posedge clk)
|
always @(posedge clk)
|
begin
|
begin
|
if ( upd_l_alu8 & exec_ixir2) ixr[7:0] <= alu8_out;
|
if ( upd_l_alu8 & exec_ixir2) ixr[7:0] <= alu8_out;
|
if ( upd_l_src_pqr & exec_ixir2) ixr[7:0] <= src_pqr20;
|
if ( upd_l_src_pqr & exec_ixir2) ixr[7:0] <= src_pqr20;
|
if ( up_l_add16 & exec_ixir2) ixr[7:0] <= add16[7:0];
|
if ( up_l_add16 & exec_ixir2) ixr[7:0] <= add16[7:0];
|
if ( LDsHL_NN == ir2 & exec_ixir2) ixr[7:0] <= nn[7:0];
|
if ( LDsHL_NN == ir2 & exec_ixir2) ixr[7:0] <= nn[7:0];
|
if ( LDsHL_6NN7== ir2 & exec_ixir2) ixr[7:0] <= nn[7:0];
|
if ( LDsHL_6NN7== ir2 & exec_ixir2) ixr[7:0] <= nn[7:0];
|
if ( POPsHL == ir2 & exec_ixir2) ixr[7:0] <= nn[7:0];
|
if ( POPsHL == ir2 & exec_ixir2) ixr[7:0] <= nn[7:0];
|
if ( EXs6SP7_HL== ir2 & exec_ixir2) ixr[7:0] <= nn[7:0];
|
if ( EXs6SP7_HL== ir2 & exec_ixir2) ixr[7:0] <= nn[7:0];
|
|
|
if ( LDsL_N == ir2 & exec_ixir2) ixr[7:0] <= nn[7:0];
|
if ( LDsL_N == ir2 & exec_ixir2) ixr[7:0] <= nn[15:8];
|
if (ir2[2:0] == REG8_L &
|
if (ir2[2:0] == REG8_L &
|
bit_alu_act & exec_ixir2) ixr[7:0] <= bit_alu;
|
bit_alu_act & exec_ixir2) ixr[7:0] <= bit_alu;
|
if (ir2[2:0] == REG8_L &
|
if (ir2[2:0] == REG8_L &
|
sh_alu_act & exec_ixir2) ixr[7:0] <= sh_alu;
|
sh_alu_act & exec_ixir2) ixr[7:0] <= sh_alu;
|
|
|
| Line 960... |
Line 963... |
if ( LDsHL_NN == ir2 & exec_ixir2) ixr[15:8] <= nn[15:8];
|
if ( LDsHL_NN == ir2 & exec_ixir2) ixr[15:8] <= nn[15:8];
|
if ( LDsHL_6NN7== ir2 & exec_ixir2) ixr[15:8] <= nn[15:8];
|
if ( LDsHL_6NN7== ir2 & exec_ixir2) ixr[15:8] <= nn[15:8];
|
if ( POPsHL == ir2 & exec_ixir2) ixr[15:8] <= nn[15:8];
|
if ( POPsHL == ir2 & exec_ixir2) ixr[15:8] <= nn[15:8];
|
if ( EXs6SP7_HL== ir2 & exec_ixir2) ixr[15:8] <= nn[15:8];
|
if ( EXs6SP7_HL== ir2 & exec_ixir2) ixr[15:8] <= nn[15:8];
|
|
|
if ( LDsH_N == ir2 & exec_ixir2) ixr[15:8] <= nn[7:0];
|
if ( LDsH_N == ir2 & exec_ixir2) ixr[15:8] <= nn[15:8];
|
if (ir2[2:0] == REG8_H &
|
if (ir2[2:0] == REG8_H &
|
bit_alu_act & exec_ixir2) ixr[15:8] <= bit_alu;
|
bit_alu_act & exec_ixir2) ixr[15:8] <= bit_alu;
|
if (ir2[2:0] == REG8_H &
|
if (ir2[2:0] == REG8_H &
|
sh_alu_act & exec_ixir2) ixr[15:8] <= sh_alu;
|
sh_alu_act & exec_ixir2) ixr[15:8] <= sh_alu;
|
|
|
end
|
end
|
|
|
//------------------------ iyr ---------------------------------------------
|
//------------------------ iyr ---------------------------------------------
|
wire exec_iyir2 = exec_ir2 & fd_grp;
|
wire exec_iyir2 = exec_ir2 & ir2fd;
|
always @(posedge clk)
|
always @(posedge clk)
|
begin
|
begin
|
if ( upd_l_alu8 & exec_iyir2) iyr[7:0] <= alu8_out;
|
if ( upd_l_alu8 & exec_iyir2) iyr[7:0] <= alu8_out;
|
if ( upd_l_src_pqr & exec_iyir2) iyr[7:0] <= src_pqr20;
|
if ( upd_l_src_pqr & exec_iyir2) iyr[7:0] <= src_pqr20;
|
if ( up_l_add16 & exec_iyir2) iyr[7:0] <= add16[7:0];
|
if ( up_l_add16 & exec_iyir2) iyr[7:0] <= add16[7:0];
|
if ( LDsHL_NN == ir2 & exec_iyir2) iyr[7:0] <= nn[7:0];
|
if ( LDsHL_NN == ir2 & exec_iyir2) iyr[7:0] <= nn[7:0];
|
if ( LDsHL_6NN7== ir2 & exec_iyir2) iyr[7:0] <= nn[7:0];
|
if ( LDsHL_6NN7== ir2 & exec_iyir2) iyr[7:0] <= nn[7:0];
|
if ( POPsHL == ir2 & exec_iyir2) iyr[7:0] <= nn[7:0];
|
if ( POPsHL == ir2 & exec_iyir2) iyr[7:0] <= nn[7:0];
|
if ( EXs6SP7_HL== ir2 & exec_iyir2) iyr[7:0] <= nn[7:0];
|
if ( EXs6SP7_HL== ir2 & exec_iyir2) iyr[7:0] <= nn[7:0];
|
|
|
if ( LDsL_N == ir2 & exec_iyir2) iyr[7:0] <= nn[7:0];
|
if ( LDsL_N == ir2 & exec_iyir2) iyr[7:0] <= nn[15:8];
|
if (ir2[2:0] == REG8_L &
|
if (ir2[2:0] == REG8_L &
|
bit_alu_act & exec_iyir2) iyr[7:0] <= bit_alu;
|
bit_alu_act & exec_iyir2) iyr[7:0] <= bit_alu;
|
if (ir2[2:0] == REG8_L &
|
if (ir2[2:0] == REG8_L &
|
sh_alu_act & exec_iyir2) iyr[7:0] <= sh_alu;
|
sh_alu_act & exec_iyir2) iyr[7:0] <= sh_alu;
|
|
|
| Line 998... |
Line 1001... |
if ( LDsHL_NN == ir2 & exec_iyir2) iyr[15:8] <= nn[15:8];
|
if ( LDsHL_NN == ir2 & exec_iyir2) iyr[15:8] <= nn[15:8];
|
if ( LDsHL_6NN7== ir2 & exec_iyir2) iyr[15:8] <= nn[15:8];
|
if ( LDsHL_6NN7== ir2 & exec_iyir2) iyr[15:8] <= nn[15:8];
|
if ( POPsHL == ir2 & exec_iyir2) iyr[15:8] <= nn[15:8];
|
if ( POPsHL == ir2 & exec_iyir2) iyr[15:8] <= nn[15:8];
|
if ( EXs6SP7_HL== ir2 & exec_iyir2) iyr[15:8] <= nn[15:8];
|
if ( EXs6SP7_HL== ir2 & exec_iyir2) iyr[15:8] <= nn[15:8];
|
|
|
if ( LDsH_N == ir2 & exec_iyir2) iyr[15:8] <= nn[7:0];
|
if ( LDsH_N == ir2 & exec_iyir2) iyr[15:8] <= nn[15:8];
|
if (ir2[2:0] == REG8_H &
|
if (ir2[2:0] == REG8_H &
|
bit_alu_act & exec_iyir2) iyr[15:8] <= bit_alu;
|
bit_alu_act & exec_iyir2) iyr[15:8] <= bit_alu;
|
if (ir2[2:0] == REG8_H &
|
if (ir2[2:0] == REG8_H &
|
sh_alu_act & exec_iyir2) iyr[15:8] <= sh_alu;
|
sh_alu_act & exec_iyir2) iyr[15:8] <= sh_alu;
|
|
|
| Line 1069... |
Line 1072... |
ADDsA_D == ir2 | CPsD == ir2 | SBCsC == ir2 | XORsD == ir2 | INCsE == ir2 |
|
ADDsA_D == ir2 | CPsD == ir2 | SBCsC == ir2 | XORsD == ir2 | INCsE == ir2 |
|
ADDsA_E == ir2 | CPsE == ir2 | SBCsD == ir2 | XORsE == ir2 | INCsH == ir2 |
|
ADDsA_E == ir2 | CPsE == ir2 | SBCsD == ir2 | XORsE == ir2 | INCsH == ir2 |
|
ADDsA_H == ir2 | CPsH == ir2 | SBCsE == ir2 | XORsH == ir2 | INCsL == ir2 |
|
ADDsA_H == ir2 | CPsH == ir2 | SBCsE == ir2 | XORsH == ir2 | INCsL == ir2 |
|
ADDsA_L == ir2 | CPsL == ir2 | SBCsH == ir2 | XORsL == ir2 | INCs6HL7 == ir2 |
|
ADDsA_L == ir2 | CPsL == ir2 | SBCsH == ir2 | XORsL == ir2 | INCs6HL7 == ir2 |
|
ADDsA_6HL7== ir2| CPs6HL7 ==ir2 | SBCsL == ir2 | XORs6HL7 == ir2 | DECs6HL7 == ir2 |
|
ADDsA_6HL7== ir2| CPs6HL7 ==ir2 | SBCsL == ir2 | XORs6HL7 == ir2 | DECs6HL7 == ir2 |
|
|
CPsN == ir2 |
|
ED_NEG == {ir2[9:6],ir2[2:0]} ; //7'b1001___100, A<= -A
|
ED_NEG == {ir2[9:6],ir2[2:0]} ; //7'b1001___100, A<= -A
|
|
|
|
|
|
|
// update h n c (f5, f3) from alu16
|
// update h n c (f5, f3) from alu16
|
| Line 1112... |
Line 1116... |
CB_SRL == ir2[9:3] ; // these must be compaired with ir2[9:3]
|
CB_SRL == ir2[9:3] ; // these must be compaired with ir2[9:3]
|
|
|
// pretty nomal stuff here
|
// pretty nomal stuff here
|
//CB_BIT = 4'b01_01, // these must be compaired with ir2[9:6]
|
//CB_BIT = 4'b01_01, // these must be compaired with ir2[9:6]
|
// which alu? -- done from alu8
|
// which alu? -- done from alu8
|
//ED_NEG = 5'b01___100, // compair with {ir2[7:6],ir2[2:0]} all A<= -A
|
//ED_NEG = 5'b01___100, // compair with {ir2[9:6],ir2[2:0]} all A<= -A
|
|
|
// rmw 8 types these handled by standard INC and DEC logic done.
|
// rmw 8 types these handled by standard INC and DEC logic done.
|
//INCs6HL7 = 'h34,// INC (HL) ; 34
|
//INCs6HL7 = 'h34,// INC (HL) ; 34
|
//DECs6HL7 = 'h35,// DEC (HL) ; 35
|
//DECs6HL7 = 'h35,// DEC (HL) ; 35
|
|
|
| Line 1144... |
Line 1148... |
//ED_OUTI = 'hA3// OUTI ; ED A3 (Cio) <-(HL++) , B--
|
//ED_OUTI = 'hA3// OUTI ; ED A3 (Cio) <-(HL++) , B--
|
//ED_OUTD = 'hAB// OUTD ; ED AB (Cio) <-(HL--) , B--
|
//ED_OUTD = 'hAB// OUTD ; ED AB (Cio) <-(HL--) , B--
|
//ED_OTIR = 'hB3// OTIR ; ED B3 (Cio) <-(HL++) , B-- rpt if(|B)
|
//ED_OTIR = 'hB3// OTIR ; ED B3 (Cio) <-(HL++) , B-- rpt if(|B)
|
//ED_OTDR = 'hBB// OTDR ; ED BB (Cio) <-(HL--) , B-- rpt if(|B)
|
//ED_OTDR = 'hBB// OTDR ; ED BB (Cio) <-(HL--) , B-- rpt if(|B)
|
|
|
//ED_INsREG_6C7 = 5'b01___000,// compair with {ir2[7:6],ir2[2:0]} really (BCio)
|
//ED_INsREG_6C7 = 5'b01___000,// compair with {ir2[9:6],ir2[2:0]} really (BCio)
|
|
|
|
|
|
|
// special problems -- lol more special problems ????
|
// special problems -- lol more special problems ????
|
//CCF = 'h3F,// CCF ; 3F // h<=c c<=~C N<=0 F3,F5?
|
//CCF = 'h3F,// CCF ; 3F // h<=c c<=~C N<=0 F3,F5?
|
| Line 1171... |
Line 1175... |
( upd_fr_edadd16) |
|
( upd_fr_edadd16) |
|
( upd_fr_sh ) |
|
( upd_fr_sh ) |
|
( upd_fr_cbsh ) |
|
( upd_fr_cbsh ) |
|
(CB_BIT == ir2[9:6]) |
|
(CB_BIT == ir2[9:6]) |
|
( ed_blk_cp ) |
|
( ed_blk_cp ) |
|
(ED_INsREG_6C7 == {ir2[7:6],ir2[2:0]}) |
|
(ED_INsREG_6C7 == {ir2[9:6],ir2[2:0]}) |
|
(CCF == ir2 ) |
|
(CCF == ir2 ) |
|
(CPL == ir2 ) |
|
(CPL == ir2 ) |
|
(DAA == ir2 ) |
|
(DAA == ir2 ) |
|
(SCF == ir2 ) |
|
(SCF == ir2 ) |
|
(ED_RRD == ir2) |
|
(ED_RRD == ir2) |
|
| Line 1200... |
Line 1204... |
sh_alu[3], ~^sh_alu, 1'b0, sh_cry};
|
sh_alu[3], ~^sh_alu, 1'b0, sh_cry};
|
if (CB_BIT == ir2[9:6]) fr <={bit_alu[7], ~|bit_alu, bit_alu[5], 1'b1, //no idea why hf<=1
|
if (CB_BIT == ir2[9:6]) fr <={bit_alu[7], ~|bit_alu, bit_alu[5], 1'b1, //no idea why hf<=1
|
bit_alu[3], ~|bit_alu, 1'b0 , cf };// pvf == zf ???
|
bit_alu[3], ~|bit_alu, 1'b0 , cf };// pvf == zf ???
|
if ( ed_blk_cp ) fr <= {alu8_out[7], ~|alu8_out, alu8_out[5], alu8_hcry,//std a-n stuff
|
if ( ed_blk_cp ) fr <= {alu8_out[7], ~|alu8_out, alu8_out[5], alu8_hcry,//std a-n stuff
|
alu8_out[3], alu8_out[7], 1'b1, cf }; //cept nf and cf
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alu8_out[3], alu8_out[7], 1'b1, cf }; //cept nf and cf
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if (ED_INsREG_6C7 == {ir2[7:6],ir2[2:0]})
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if (ED_INsREG_6C7 == {ir2[9:6],ir2[2:0]})
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fr <= {nn[7], ~|nn[7:0], nn[5], 1'b0, nn[3], ~^nn[7:0], 1'b0, cf};
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fr <= {nn[7], ~|nn[7:0], nn[5], 1'b0, nn[3], ~^nn[7:0], 1'b0, cf};
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if (CCF == ir2 ) fr <= {sf, zf, f5f, cf, f3f, pvf, nf, ~cf};
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if (CCF == ir2 ) fr <= {sf, zf, f5f, cf, f3f, pvf, nf, ~cf};
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if (CPL == ir2 ) fr <= {sf, zf, ar[5], 1'b1, ar[3], pvf, 1'b1, cf};
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if (CPL == ir2 ) fr <= {sf, zf, ar[5], 1'b1, ar[3], pvf, 1'b1, cf};
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if (DAA == ir2 ) fr <= {daa_alu[7], ~|daa_alu, daa_alu[5], 1'b0, // hf sb (logically) 0
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if (DAA == ir2 ) fr <= {daa_alu[7], ~|daa_alu, daa_alu[5], 1'b0, // hf sb (logically) 0
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daa_alu[3], ~^daa_alu, nf, daa_cry };
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daa_alu[3], ~^daa_alu, nf, daa_cry };
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