| Line 69... |
Line 69... |
// the intention is that even if the synthesizer is pretty primitive -- reasonably fast hardware
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// the intention is that even if the synthesizer is pretty primitive -- reasonably fast hardware
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// will be produced.
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// will be produced.
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//
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//
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//-------1---------2---------3--------CVS Log -----------------------7---------8---------9--------0
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//-------1---------2---------3--------CVS Log -----------------------7---------8---------9--------0
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//
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//
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// $Id: z80_inst_exec.v,v 1.4 2004-05-21 02:51:25 bporcella Exp $
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// $Id: z80_inst_exec.v,v 1.5 2007-10-02 20:25:12 bporcella Exp $
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//
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//
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// $Date: 2004-05-21 02:51:25 $
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// $Date: 2007-10-02 20:25:12 $
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// $Revision: 1.4 $
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// $Revision: 1.5 $
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// $Author: bporcella $
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// $Author: bporcella $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2004/05/21 02:51:25 bporcella
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// inst test got to the worked macro
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//
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// Revision 1.3 2004/05/18 22:31:21 bporcella
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// Revision 1.3 2004/05/18 22:31:21 bporcella
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// instruction test getting to final stages
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// instruction test getting to final stages
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//
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//
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// Revision 1.2 2004/05/13 14:58:53 bporcella
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// Revision 1.2 2004/05/13 14:58:53 bporcella
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// testbed built and verification in progress
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// testbed built and verification in progress
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| Line 810... |
Line 813... |
if ( up_e_src_pqr & exec_ir2) er <= src_pqr20;
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if ( up_e_src_pqr & exec_ir2) er <= src_pqr20;
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if ( up_e_add16 & exec_ir2) er <= add16[7:0];
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if ( up_e_add16 & exec_ir2) er <= add16[7:0];
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if ( LDsDE_NN == ir2 & exec_ir2) er <= nn[7:0];
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if ( LDsDE_NN == ir2 & exec_ir2) er <= nn[7:0];
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if ( POPsDE == ir2 & exec_ir2) er <= nn[7:0];
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if ( POPsDE == ir2 & exec_ir2) er <= nn[7:0];
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if ( EXX == ir2 & exec_ir2) er <= ep;
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if ( EXX == ir2 & exec_ir2) er <= ep;
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if ( EXsDE_HL == ir2 & exec_ir2) er <= hr;
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if ( EXsDE_HL == ir2 & exec_ir2) er <= lr; // hharte was er <= hr
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if ( LDsE_N == ir2 & exec_ir2) er <= nn[15:8];
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if ( LDsE_N == ir2 & exec_ir2) er <= nn[15:8];
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if (ir2[2:0] == REG8_E &
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if (ir2[2:0] == REG8_E &
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bit_alu_act & exec_ir2) er <= bit_alu;
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bit_alu_act & exec_ir2) er <= bit_alu;
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if (ir2[2:0] == REG8_E &
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if (ir2[2:0] == REG8_E &
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sh_alu_act & exec_ir2) er <= sh_alu;
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sh_alu_act & exec_ir2) er <= sh_alu;
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