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Line 36... |
//// POSSIBILITY OF SUCH DAMAGE. ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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//// ////
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///////////////////////////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: z80_testbed.v,v 1.2 2004-05-18 22:31:21 bporcella Exp $
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// $Id: z80_testbed.v,v 1.3 2004-05-21 02:51:25 bporcella Exp $
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//
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//
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// $Date: 2004-05-18 22:31:21 $
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// $Date: 2004-05-21 02:51:25 $
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// $Revision: 1.2 $
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// $Revision: 1.3 $
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// $Author: bporcella $
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// $Author: bporcella $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2004/05/18 22:31:21 bporcella
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// instruction test getting to final stages
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//
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// Revision 1.1 2004/05/13 14:57:35 bporcella
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// Revision 1.1 2004/05/13 14:57:35 bporcella
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// testbed files
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// testbed files
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//
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//
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// Revision 1.1.1.1 2004/04/13 23:47:42 bporcella
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// Revision 1.1.1.1 2004/04/13 23:47:42 bporcella
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// import first files
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// import first files
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| Line 81... |
Line 84... |
.wb_we_o(wb_we),
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.wb_we_o(wb_we),
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.wb_adr_o(wb_adr),
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.wb_adr_o(wb_adr),
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.wb_tga_o(wb_tga),
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.wb_tga_o(wb_tga),
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.wb_ack_i(ack),
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.wb_ack_i(ack),
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.wb_clk_i(clk),
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.wb_clk_i(clk),
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.wb_dat_i(8'b0),
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.wb_dat_i(io_i),
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.wb_rst_i(rst),
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.wb_rst_i(rst),
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.bist_ack_o(bist_ack),
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.bist_ack_o(bist_ack),
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.bist_err_o(bist_err),
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.bist_err_o(bist_err),
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.bist_req_i(bist_req),
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.bist_req_i(bist_req),
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.int_req_i(1'b0) // initial test inst test only
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.int_req_i(1'b0) // initial test inst test only
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| Line 95... |
Line 98... |
reg ack;
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reg ack;
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wire [1:0] wb_tga;
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wire [1:0] wb_tga;
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wire [15:0] wb_adr;
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wire [15:0] wb_adr;
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wire wb_stb, wb_cyc, wb_we;
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wire wb_stb, wb_cyc, wb_we;
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wire [7:0] wb_dat;
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wire [7:0] wb_dat;
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wire [7:0] io_i;
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reg [7:0] out_state;
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parameter TAG_IO = 2'b01, // need to review general wb usage to undrstand how best to
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parameter TAG_IO = 2'b01, // need to review general wb usage to undrstand how best to
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TAG_INT = 2'b10; // document this.
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TAG_INT = 2'b10; // document this.
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// a pretty simple output device
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parameter MY_IO_ADR = 8'h10 ;
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// ----------------- a pretty simple I/O device -------
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// output simply displays the data written --
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// input cycles through
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// various interesting data patterens as used by the instruction test
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// namely 7f 55 80 0 ff aa
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assign io_i = (wb_adr[7:0] == MY_IO_ADR) & wb_stb & wb_cyc & (wb_tga == TAG_IO) & !wb_we ?
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out_state : 8'hz;
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wire a2me = (wb_adr[7:0] == MY_IO_ADR) & wb_stb & wb_cyc & (wb_tga == TAG_IO);
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wire wr2me = (wb_adr[7:0] == 8'h10) & wb_stb & wb_cyc & (wb_tga == TAG_IO) & wb_we;
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst ) ack <= 1'b0;
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if (rst ) ack <= 1'b0;
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else if (wr2me & !ack)
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else if (a2me & !ack)
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begin
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begin
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ack <= 1'b1;
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ack <= 1'b1;
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$write("%s",wb_dat);
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if (wb_we) $write("%s",wb_dat);
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end
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end
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else ack <= 1'b0;
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else ack <= 1'b0;
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end
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always @(posedge clk or posedge rst)
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begin
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if (rst) out_state <= 8'h7f;
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else if (a2me & !wb_we & ack)
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case (out_state)
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8'h7f: out_state <= 8'h55 ;
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8'h55: out_state <= 8'h80 ;
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8'h80: out_state <= 8'h00 ;
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8'h00: out_state <= 8'hff ;
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8'hff: out_state <= 8'haa ;
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8'haa: out_state <= 8'h7f ;
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default: out_state <= 8'h7f ;
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endcase
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end
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end
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initial
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initial
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begin
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begin
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clk = 0;
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clk = 0;
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// timeout if u hang up -- always a good idea.
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// timeout if u hang up -- always a good idea.
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#500000 $finish;
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#500000 $finish;
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