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[/] [wb_z80/] [trunk/] [rtl/] [z80_testbed.v] - Diff between revs 27 and 32
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| Rev 27 |
Rev 32 |
| Line 36... |
Line 36... |
//// POSSIBILITY OF SUCH DAMAGE. ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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//// ////
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///////////////////////////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: z80_testbed.v,v 1.4 2004-05-27 14:25:04 bporcella Exp $
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// $Id: z80_testbed.v,v 1.5 2007-10-02 20:25:12 bporcella Exp $
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//
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//
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// $Date: 2004-05-27 14:25:04 $
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// $Date: 2007-10-02 20:25:12 $
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// $Revision: 1.4 $
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// $Revision: 1.5 $
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// $Author: bporcella $
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// $Author: bporcella $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2004/05/27 14:25:04 bporcella
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// Instruction test (with interrupts) runs!!!
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//
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// Revision 1.3 2004/05/21 02:51:25 bporcella
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// Revision 1.3 2004/05/21 02:51:25 bporcella
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// inst test got to the worked macro
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// inst test got to the worked macro
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//
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//
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// Revision 1.2 2004/05/18 22:31:21 bporcella
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// Revision 1.2 2004/05/18 22:31:21 bporcella
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// instruction test getting to final stages
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// instruction test getting to final stages
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| Line 76... |
Line 79... |
wire bist_err;
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wire bist_err;
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//------- CAUTION TEST RESULTS DEPEND ON INITIAL CONDITIONS -------
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//------- CAUTION TEST RESULTS DEPEND ON INITIAL CONDITIONS -------
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// bist will not pass if some of these imputs are not as specified.
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// bist will not pass if some of these inputs are not as specified.
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//
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//
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z80_core_top i_z80_core_top(
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z80_core_top i_z80_core_top(
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.wb_dat_o(),
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.wb_dat_o(),
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.wb_stb_o(),
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.wb_stb_o(),
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.wb_cyc_o(),
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.wb_cyc_o(),
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