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https://opencores.org/ocsvn/wbddr3/wbddr3/trunk
[/] [wbddr3/] [trunk/] [bench/] [cpp/] [ddrsdramsim.cpp] - Diff between revs 9 and 12
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| Rev 9 |
Rev 12 |
| Line 46... |
Line 46... |
ckREFI = 1560, // 7.8us @ 200MHz = 7.8e-6 * 200e6 = 1560
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ckREFI = 1560, // 7.8us @ 200MHz = 7.8e-6 * 200e6 = 1560
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ckREFIn = nREF*ckREFI - (nREF-1) * ckRFC;
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ckREFIn = nREF*ckREFI - (nREF-1) * ckRFC;
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#include "ddrsdramsim.h"
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#include "ddrsdramsim.h"
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void BANKINFO::tick(int cmd, unsigned addr) {
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void BANKINFO::tick(int cmd, unsigned addr) {
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if (m_wcounter)
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m_wcounter--;
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switch(cmd) {
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switch(cmd) {
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case DDR_PRECHARGE:
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case DDR_PRECHARGE:
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m_state = 6;
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m_state = 6;
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// While the specification allows precharging an already
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// While the specification allows precharging an already
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// precharged bank, we can keep that from happening
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// precharged bank, we can keep that from happening
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| Line 57... |
Line 59... |
// assert(m_state&7);
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// assert(m_state&7);
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// Only problem is, this will currently break our
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// Only problem is, this will currently break our
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// refresh logic.
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// refresh logic.
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break;
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break;
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case DDR_ACTIVATE:
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case DDR_ACTIVATE:
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assert(m_wcounter == 0);
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m_state = 1;
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m_state = 1;
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m_row = addr & 0x7fff;
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m_row = addr & 0x7fff;
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break;
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break;
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case DDR_READ: case DDR_WRITE:
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case DDR_READ: case DDR_WRITE:
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if (DDR_READ)
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assert(m_wcounter == 0);
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else
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m_wcounter = 3+4+4;
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printf("BANK::R/W Request, m_state = %d\n", m_state);
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printf("BANK::R/W Request, m_state = %d\n", m_state);
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assert((m_state&7) == 7);
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assert((m_state&7) == 7);
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break;
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break;
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case DDR_ZQS:
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case DDR_ZQS:
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assert((m_state&7) == 0);
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assert((m_state&7) == 0);
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