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Line 37... |
//
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//
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#include <stdio.h>
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#include <stdio.h>
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#include <assert.h>
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#include <assert.h>
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const unsigned ckCL = 5,
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const unsigned ckCL = 5,
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ckRC = 3;
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ckRC = 3,
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ckRFC = 320, // Clocks from refresh to activate
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nREF = 4,
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ckREFI = 1560, // 7.8us @ 200MHz = 7.8e-6 * 200e6 = 1560
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ckREFIn = nREF*ckREFI - (nREF-1) * ckRFC;
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#include "ddrsdramsim.h"
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#include "ddrsdramsim.h"
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void BANKINFO::tick(int cmd, unsigned addr) {
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void BANKINFO::tick(int cmd, unsigned addr) {
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switch(cmd) {
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switch(cmd) {
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case DDR_PRECHARGE:
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case DDR_PRECHARGE:
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m_state <<= 1;
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m_state = 6;
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// m_state |= 1;
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m_state &= 6;
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break;
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break;
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case DDR_ACTIVATE:
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case DDR_ACTIVATE:
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m_state <<= 1;
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m_state = 1;
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m_state |= 1;
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m_state &= 7;
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m_row = addr & 0x7fff;
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m_row = addr & 0x7fff;
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break;
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break;
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case DDR_READ: case DDR_WRITE:
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case DDR_READ: case DDR_WRITE:
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printf("BANK::R/W Request, m_state = %d\n", m_state);
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assert((m_state&7) == 7);
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assert((m_state&7) == 7);
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break;
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break;
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case DDR_ZQS:
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case DDR_ZQS:
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assert((m_state&7) == 0);
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assert((m_state&7) == 0);
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break;
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break;
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Line 110... |
m_reset_counts = 0;
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m_reset_counts = 0;
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m_reset_state = 2;
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m_reset_state = 2;
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} break;
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} break;
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case 2:
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case 2:
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m_reset_counts++;
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m_reset_counts++;
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assert(cke);
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if (cmd != DDR_NOOP) {
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if (cmd != DDR_NOOP) {
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assert(m_reset_counts > 147);
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assert(m_reset_counts > 147);
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m_reset_counts = 0;
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m_reset_counts = 0;
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m_reset_state = 3;
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m_reset_state = 3;
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assert(cmd == DDR_MRSET);
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assert(cmd == DDR_MRSET);
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assert(ba == 2);
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assert(ba == 2);
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assert(addr == 0x040);
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assert(addr == 0x040);
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} break;
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} break;
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case 3:
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case 3:
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m_reset_counts++;
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m_reset_counts++;
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assert(cke);
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if (cmd != DDR_NOOP) {
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if (cmd != DDR_NOOP) {
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// assert(m_reset_counts > 3);
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// assert(m_reset_counts > 3);
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m_reset_counts = 0;
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m_reset_counts = 0;
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m_reset_state = 4;
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m_reset_state = 4;
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assert(cmd == DDR_MRSET);
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assert(cmd == DDR_MRSET);
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// assert(ba == 1);
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// assert(ba == 1);
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// assert(addr == 0x847);
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// assert(addr == 0x847);
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} break;
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} break;
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case 4:
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case 4:
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m_reset_counts++;
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m_reset_counts++;
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assert(cke);
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if (cmd != DDR_NOOP) {
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if (cmd != DDR_NOOP) {
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printf("DDR3-SDRAM::RESET-CMD[4]: %d:%08x[%d]@0x%04x\n", cmd, m_reset_counts, ba, addr);
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printf("DDR3-SDRAM::RESET-CMD[4]: %d:%08x[%d]@0x%04x\n", cmd, m_reset_counts, ba, addr);
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assert(m_reset_counts > 3);
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assert(m_reset_counts > 3);
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m_reset_counts = 0;
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m_reset_counts = 0;
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m_reset_state = 5;
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m_reset_state = 5;
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Line 144... |
assert(ba == 0);
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assert(ba == 0);
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assert(addr == 0x210);
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assert(addr == 0x210);
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} break;
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} break;
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case 5:
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case 5:
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m_reset_counts++;
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m_reset_counts++;
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assert(cke);
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if (cmd != DDR_NOOP) {
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if (cmd != DDR_NOOP) {
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printf("DDR3-SDRAM::RESET-CMD[5]: %d:%08x[%d]@0x%04x\n", cmd, m_reset_counts, ba, addr);
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printf("DDR3-SDRAM::RESET-CMD[5]: %d:%08x[%d]@0x%04x\n", cmd, m_reset_counts, ba, addr);
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assert(m_reset_counts > 11);
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assert(m_reset_counts > 11);
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m_reset_counts = 0;
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m_reset_counts = 0;
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m_reset_state = 6;
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m_reset_state = 6;
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assert(cmd == DDR_ZQS);
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assert(cmd == DDR_ZQS);
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assert(addr == 0x400);
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assert(addr == 0x400);
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} break;
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} break;
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case 6:
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case 6:
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m_reset_counts++;
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m_reset_counts++;
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assert(cke);
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if (cmd != DDR_NOOP) {
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if (cmd != DDR_NOOP) {
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printf("DDR3-SDRAM::RESET-CMD[6]: %d:%08x[%d]@0x%04x\n", cmd, m_reset_counts, ba, addr);
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printf("DDR3-SDRAM::RESET-CMD[6]: %d:%08x[%d]@0x%04x\n", cmd, m_reset_counts, ba, addr);
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assert(m_reset_counts > 512);
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assert(m_reset_counts > 512);
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m_reset_counts = 0;
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m_reset_counts = 0;
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m_reset_state = 7;
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m_reset_state = 7;
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assert(cmd == DDR_PRECHARGE);
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assert(cmd == DDR_PRECHARGE);
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assert(addr == 0x400);
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assert(addr == 0x400);
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} break;
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} break;
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case 7:
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case 7:
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m_reset_counts++;
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m_reset_counts++;
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assert(cke);
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if (cmd != DDR_NOOP) {
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if (cmd != DDR_NOOP) {
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printf("DDR3-SDRAM::RESET-CMD[7]: %d:%08x[%d]@0x%04x\n", cmd, m_reset_counts, ba, addr);
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printf("DDR3-SDRAM::RESET-CMD[7]: %d:%08x[%d]@0x%04x\n", cmd, m_reset_counts, ba, addr);
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assert(m_reset_counts > 3);
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assert(m_reset_counts > 3);
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m_reset_counts = 0;
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m_reset_counts = 0;
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m_reset_state = 8;
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m_reset_state = 8;
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assert(cmd == DDR_REFRESH);
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assert(cmd == DDR_REFRESH);
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m_clocks_since_refresh = 0;
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} break;
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} break;
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case 8:
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case 8:
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m_reset_counts++;
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m_reset_counts++;
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assert(cke);
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assert(cmd == DDR_NOOP);
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assert(cmd == DDR_NOOP);
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if (m_reset_counts > 140) {
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if (m_reset_counts > 140) {
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m_reset_state = 16;
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m_reset_state = 16;
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printf("DDR3-SDRAM: Leaving reset state\n");
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printf("DDR3-SDRAM: Leaving reset state\n");
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}
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}
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Line 190... |
break;
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break;
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}
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}
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gbl_state = m_reset_state;
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gbl_state = m_reset_state;
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gbl_counts= m_reset_counts;
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gbl_counts= m_reset_counts;
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} else if (cke == 0) {
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m_nrefresh_issued = nREF;
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} else if (!cke) {
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assert(0&&"Clock not enabled!");
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assert(0&&"Clock not enabled!");
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} else switch(cmd) {
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} else if ((cmd == DDR_REFRESH)||(m_nrefresh_issued < (int)nREF)) {
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if (DDR_REFRESH == cmd) {
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m_clocks_since_refresh = 0;
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if (m_nrefresh_issued >= (int)nREF)
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m_nrefresh_issued = 0;
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else
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m_nrefresh_issued++;
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} else {
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m_clocks_since_refresh++;
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assert(DDR_NOOP == cmd);
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}
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for(int i=0; i<NBANKS; i++)
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m_bank[i].tick(DDR_REFRESH,0);
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} else {
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// In operational mode!!
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m_clocks_since_refresh++;
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assert(m_clocks_since_refresh < (int)ckREFIn);
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switch(cmd) {
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case DDR_MRSET:
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case DDR_MRSET:
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assert(0&&"Modes should only be set in reset startup");
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assert(0&&"Modes should only be set in reset startup");
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for(int i=0; i<NBANKS; i++)
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for(int i=0; i<NBANKS; i++)
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m_bank[i].tick(DDR_MRSET,0);
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m_bank[i].tick(DDR_MRSET,0);
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break;
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break;
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case DDR_REFRESH:
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case DDR_REFRESH:
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for(int i=0; i<NBANKS; i++)
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for(int i=0; i<NBANKS; i++)
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m_bank[i].tick(DDR_REFRESH,0);
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m_bank[i].tick(DDR_REFRESH,0);
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m_clocks_since_refresh = 0;
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assert(0 && "Internal err: Refresh should be handled above");
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break;
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break;
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case DDR_PRECHARGE:
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case DDR_PRECHARGE:
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if (addr & 0x40) {
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if (addr & 0x40) {
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// Precharge all
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// Precharge all
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for(int i=0; i<NBANKS; i++)
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for(int i=0; i<NBANKS; i++)
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| Line 212... |
Line 242... |
for(int i=0; i<NBANKS; i++)
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for(int i=0; i<NBANKS; i++)
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if (i!=ba) m_bank[i].tick(DDR_NOOP,0);
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if (i!=ba) m_bank[i].tick(DDR_NOOP,0);
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break;
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break;
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case DDR_WRITE:
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case DDR_WRITE:
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{
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{
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// This SIM doesn't handle out of order writes
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assert((addr&7)==0);
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m_bank[ba].tick(DDR_WRITE, addr);
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for(int i=0; i<NBANKS; i++)
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for(int i=0; i<NBANKS; i++)
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m_bank[i].tick(DDR_WRITE,addr);
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if (i!=ba)m_bank[i].tick(DDR_NOOP,addr);
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unsigned addr = m_bank[ba].m_row;
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unsigned addr = m_bank[ba].m_row;
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addr <<= 13;
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addr <<= 13;
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addr |= ba;
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addr |= ba;
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addr <<= 10;
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addr <<= 10;
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addr |= addr;
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addr |= addr;
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| Line 245... |
Line 278... |
tp->m_used = 1;
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tp->m_used = 1;
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tp->m_read = 0;
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tp->m_read = 0;
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} break;
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} break;
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case DDR_READ:
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case DDR_READ:
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{
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{
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// This SIM doesn't handle out of order reads
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assert((addr&7)==0);
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m_bank[ba].tick(DDR_READ, addr);
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for(int i=0; i<NBANKS; i++)
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for(int i=0; i<NBANKS; i++)
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m_bank[i].tick(DDR_READ,addr);
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if (i!=ba)m_bank[i].tick(DDR_NOOP,addr);
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unsigned addr = m_bank[ba].m_row;
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unsigned addr = m_bank[ba].m_row;
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addr <<= 13;
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addr <<= 13;
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addr |= ba;
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addr |= ba;
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addr <<= 10;
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addr <<= 10;
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addr |= addr;
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addr |= addr;
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| Line 292... |
Line 328... |
default: // We are deselecteda
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default: // We are deselecteda
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for(int i=0; i<NBANKS; i++)
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for(int i=0; i<NBANKS; i++)
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m_bank[i].tick(DDR_NOOP,addr);
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m_bank[i].tick(DDR_NOOP,addr);
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break;
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break;
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}
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}
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}
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m_busloc = (m_busloc+1)&(NTIMESLOTS-1);
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m_busloc = (m_busloc+1)&(NTIMESLOTS-1);
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BUSTIMESLOT *ts = &m_bus[m_busloc];
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BUSTIMESLOT *ts = &m_bus[m_busloc];
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unsigned vl = ts->m_data;
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unsigned vl = ts->m_data;
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