| Line 48... |
Line 48... |
#include "ddrsdramsim.h"
|
#include "ddrsdramsim.h"
|
void BANKINFO::tick(int cmd, unsigned addr) {
|
void BANKINFO::tick(int cmd, unsigned addr) {
|
switch(cmd) {
|
switch(cmd) {
|
case DDR_PRECHARGE:
|
case DDR_PRECHARGE:
|
m_state = 6;
|
m_state = 6;
|
|
// While the specification allows precharging an already
|
|
// precharged bank, we can keep that from happening
|
|
// here:
|
|
// assert(m_state&7);
|
|
// Only problem is, this will currently break our
|
|
// refresh logic.
|
break;
|
break;
|
case DDR_ACTIVATE:
|
case DDR_ACTIVATE:
|
m_state = 1;
|
m_state = 1;
|
m_row = addr & 0x7fff;
|
m_row = addr & 0x7fff;
|
break;
|
break;
|
| Line 215... |
Line 221... |
} else {
|
} else {
|
// In operational mode!!
|
// In operational mode!!
|
|
|
m_clocks_since_refresh++;
|
m_clocks_since_refresh++;
|
assert(m_clocks_since_refresh < (int)ckREFIn);
|
assert(m_clocks_since_refresh < (int)ckREFIn);
|
printf("Clocks to refresh should be %4d-%4d = %4d = 0x%04x\n",
|
|
ckREFIn, m_clocks_since_refresh,
|
|
ckREFIn- m_clocks_since_refresh,
|
|
ckREFIn- m_clocks_since_refresh);
|
|
switch(cmd) {
|
switch(cmd) {
|
case DDR_MRSET:
|
case DDR_MRSET:
|
assert(0&&"Modes should only be set in reset startup");
|
assert(0&&"Modes should only be set in reset startup");
|
for(int i=0; i<NBANKS; i++)
|
for(int i=0; i<NBANKS; i++)
|
m_bank[i].tick(DDR_MRSET,0);
|
m_bank[i].tick(DDR_MRSET,0);
|
| Line 258... |
Line 260... |
assert((addr&7)==0);
|
assert((addr&7)==0);
|
m_bank[ba].tick(DDR_WRITE, addr);
|
m_bank[ba].tick(DDR_WRITE, addr);
|
for(int i=0; i<NBANKS; i++)
|
for(int i=0; i<NBANKS; i++)
|
if (i!=ba)m_bank[i].tick(DDR_NOOP,addr);
|
if (i!=ba)m_bank[i].tick(DDR_NOOP,addr);
|
unsigned caddr = m_bank[ba].m_row;
|
unsigned caddr = m_bank[ba].m_row;
|
caddr <<= 13;
|
caddr <<= 3;
|
caddr |= ba;
|
caddr |= ba;
|
caddr <<= 10;
|
caddr <<= 10;
|
caddr |= addr;
|
caddr |= addr;
|
caddr &= ~7;
|
caddr &= ~7;
|
caddr >>= 1;
|
caddr >>= 1;
|
| Line 300... |
Line 302... |
assert((addr&7)==0);
|
assert((addr&7)==0);
|
m_bank[ba].tick(DDR_READ, addr);
|
m_bank[ba].tick(DDR_READ, addr);
|
for(int i=0; i<NBANKS; i++)
|
for(int i=0; i<NBANKS; i++)
|
if (i!=ba)m_bank[i].tick(DDR_NOOP,addr);
|
if (i!=ba)m_bank[i].tick(DDR_NOOP,addr);
|
unsigned caddr = m_bank[ba].m_row;
|
unsigned caddr = m_bank[ba].m_row;
|
caddr <<= 13;
|
caddr <<= 3;
|
caddr |= ba;
|
caddr |= ba;
|
caddr <<= 10;
|
caddr <<= 10;
|
caddr |= addr;
|
caddr |= addr;
|
caddr &= ~7;
|
caddr &= ~7;
|
caddr >>= 1;
|
caddr >>= 1;
|
|
|
BUSTIMESLOT *tp;
|
BUSTIMESLOT *tp;
|
|
|
tp = &m_bus[(m_busloc+ckCL+0)&(NTIMESLOTS-1)];
|
int offset = (m_busloc+ckCL+1)&(NTIMESLOTS-1);
|
|
tp = &m_bus[(offset)&(NTIMESLOTS-1)];
|
tp->m_data = m_mem[caddr];
|
tp->m_data = m_mem[caddr];
|
tp->m_addr = caddr;
|
tp->m_addr = caddr;
|
tp->m_used = 1;
|
tp->m_used = 1;
|
tp->m_read = 1;
|
tp->m_read = 1;
|
|
|
tp = &m_bus[(m_busloc+ckCL+1)&(NTIMESLOTS-1)];
|
tp = &m_bus[(offset+1)&(NTIMESLOTS-1)];
|
tp->m_data = m_mem[caddr+1];
|
tp->m_data = m_mem[caddr+1];
|
tp->m_addr = caddr+1;
|
tp->m_addr = caddr+1;
|
tp->m_used = 1;
|
tp->m_used = 1;
|
tp->m_read = 1;
|
tp->m_read = 1;
|
|
|
tp = &m_bus[(m_busloc+ckCL+2)&(NTIMESLOTS-1)];
|
tp = &m_bus[(offset+2)&(NTIMESLOTS-1)];
|
tp->m_data = m_mem[caddr+2];
|
tp->m_data = m_mem[caddr+2];
|
tp->m_addr = caddr+2;
|
tp->m_addr = caddr+2;
|
tp->m_used = 1;
|
tp->m_used = 1;
|
tp->m_read = 1;
|
tp->m_read = 1;
|
|
|
tp = &m_bus[(m_busloc+ckCL+3)&(NTIMESLOTS-1)];
|
tp = &m_bus[(offset+3)&(NTIMESLOTS-1)];
|
tp->m_data = m_mem[caddr+3];
|
tp->m_data = m_mem[caddr+3];
|
tp->m_addr = caddr+3;
|
tp->m_addr = caddr+3;
|
tp->m_used = 1;
|
tp->m_used = 1;
|
tp->m_read = 1;
|
tp->m_read = 1;
|
} break;
|
} break;
|
