| Line 36... |
Line 36... |
//
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//
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//
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//
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#include <stdio.h>
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#include <stdio.h>
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#include <assert.h>
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#include <assert.h>
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#define PREFIX "DDR3-SDRAM"
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const unsigned ckCL = 5,
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const unsigned ckCL = 5,
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ckRC = 3,
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ckRC = 3,
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ckRFC = 320, // Clocks from refresh to activate
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ckRFC = 320, // Clocks from refresh to activate
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nREF = 4,
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nREF = 4,
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ckREFI = 1560, // 7.8us @ 200MHz = 7.8e-6 * 200e6 = 1560
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ckREFI = 1560, // 7.8us @ 200MHz = 7.8e-6 * 200e6 = 1560
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| Line 140... |
Line 141... |
} break;
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} break;
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case 4:
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case 4:
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m_reset_counts++;
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m_reset_counts++;
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assert(cke);
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assert(cke);
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if (cmd != DDR_NOOP) {
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if (cmd != DDR_NOOP) {
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printf("DDR3-SDRAM::RESET-CMD[4]: %d:%08x[%d]@0x%04x\n", cmd, m_reset_counts, ba, addr);
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printf(PREFIX "::RESET-CMD[4]: %d:%08x[%d]@0x%04x\n", cmd, m_reset_counts, ba, addr);
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assert(m_reset_counts > 3);
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assert(m_reset_counts > 3);
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m_reset_counts = 0;
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m_reset_counts = 0;
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m_reset_state = 5;
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m_reset_state = 5;
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assert(cmd == DDR_MRSET);
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assert(cmd == DDR_MRSET);
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assert(ba == 0);
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assert(ba == 0);
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| Line 152... |
Line 153... |
} break;
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} break;
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case 5:
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case 5:
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m_reset_counts++;
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m_reset_counts++;
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assert(cke);
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assert(cke);
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if (cmd != DDR_NOOP) {
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if (cmd != DDR_NOOP) {
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printf("DDR3-SDRAM::RESET-CMD[5]: %d:%08x[%d]@0x%04x\n", cmd, m_reset_counts, ba, addr);
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printf(PREFIX "::RESET-CMD[5]: %d:%08x[%d]@0x%04x\n", cmd, m_reset_counts, ba, addr);
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assert(m_reset_counts > 11);
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assert(m_reset_counts > 11);
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m_reset_counts = 0;
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m_reset_counts = 0;
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m_reset_state = 6;
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m_reset_state = 6;
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assert(cmd == DDR_ZQS);
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assert(cmd == DDR_ZQS);
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assert(addr == 0x400);
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assert(addr == 0x400);
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} break;
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} break;
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case 6:
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case 6:
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m_reset_counts++;
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m_reset_counts++;
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assert(cke);
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assert(cke);
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if (cmd != DDR_NOOP) {
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if (cmd != DDR_NOOP) {
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printf("DDR3-SDRAM::RESET-CMD[6]: %d:%08x[%d]@0x%04x\n", cmd, m_reset_counts, ba, addr);
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printf(PREFIX "::RESET-CMD[6]: %d:%08x[%d]@0x%04x\n", cmd, m_reset_counts, ba, addr);
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assert(m_reset_counts > 512);
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assert(m_reset_counts > 512);
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m_reset_counts = 0;
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m_reset_counts = 0;
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m_reset_state = 7;
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m_reset_state = 7;
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assert(cmd == DDR_PRECHARGE);
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assert(cmd == DDR_PRECHARGE);
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assert(addr == 0x400);
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assert(addr == 0x400);
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} break;
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} break;
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case 7:
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case 7:
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m_reset_counts++;
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m_reset_counts++;
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assert(cke);
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assert(cke);
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if (cmd != DDR_NOOP) {
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if (cmd != DDR_NOOP) {
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printf("DDR3-SDRAM::RESET-CMD[7]: %d:%08x[%d]@0x%04x\n", cmd, m_reset_counts, ba, addr);
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printf(PREFIX "::RESET-CMD[7]: %d:%08x[%d]@0x%04x\n", cmd, m_reset_counts, ba, addr);
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assert(m_reset_counts > 3);
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assert(m_reset_counts > 3);
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m_reset_counts = 0;
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m_reset_counts = 0;
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m_reset_state = 8;
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m_reset_state = 8;
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assert(cmd == DDR_REFRESH);
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assert(cmd == DDR_REFRESH);
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m_clocks_since_refresh = 0;
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m_clocks_since_refresh = 0;
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| Line 187... |
Line 188... |
m_reset_counts++;
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m_reset_counts++;
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assert(cke);
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assert(cke);
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assert(cmd == DDR_NOOP);
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assert(cmd == DDR_NOOP);
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if (m_reset_counts > 140) {
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if (m_reset_counts > 140) {
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m_reset_state = 16;
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m_reset_state = 16;
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printf("DDR3-SDRAM: Leaving reset state\n");
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printf(PREFIX ": Leaving reset state\n");
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}
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}
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break;
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break;
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default:
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default:
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break;
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break;
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}
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}
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| Line 215... |
Line 216... |
}
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}
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for(int i=0; i<NBANKS; i++)
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for(int i=0; i<NBANKS; i++)
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m_bank[i].tick(DDR_REFRESH,0);
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m_bank[i].tick(DDR_REFRESH,0);
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if (m_nrefresh_issued == nREF)
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if (m_nrefresh_issued == nREF)
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printf("DDRSDRAM::Refresh cycle complete\n");
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printf(PREFIX "::Refresh cycle complete\n");
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} else {
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} else {
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// In operational mode!!
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// In operational mode!!
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m_clocks_since_refresh++;
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m_clocks_since_refresh++;
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assert(m_clocks_since_refresh < (int)ckREFIn);
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assert(m_clocks_since_refresh < (int)ckREFIn);
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| Line 246... |
Line 247... |
if (ba != i)
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if (ba != i)
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m_bank[i].tick(DDR_NOOP,0);
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m_bank[i].tick(DDR_NOOP,0);
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}
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}
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break;
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break;
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case DDR_ACTIVATE:
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case DDR_ACTIVATE:
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printf("DDRSIM::ACTIVE, clocks_since_refresh = %d >= %d\n", m_clocks_since_refresh, ckRFC);
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assert(m_clocks_since_refresh >= (int)ckRFC);
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assert(m_clocks_since_refresh >= (int)ckRFC);
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m_bank[ba].tick(DDR_ACTIVATE,addr);
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m_bank[ba].tick(DDR_ACTIVATE,addr);
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for(int i=0; i<NBANKS; i++)
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for(int i=0; i<NBANKS; i++)
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if (i!=ba) m_bank[i].tick(DDR_NOOP,0);
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if (i!=ba) m_bank[i].tick(DDR_NOOP,0);
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break;
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break;
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| Line 267... |
Line 267... |
caddr <<= 10;
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caddr <<= 10;
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caddr |= addr;
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caddr |= addr;
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caddr &= ~7;
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caddr &= ~7;
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caddr >>= 1;
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caddr >>= 1;
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printf("DDRSDRAM::WRITE ADDR = %04x|%d|%04x|%d -> %06x\n",
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m_bank[ba].m_row, ba, addr, 0, caddr);
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BUSTIMESLOT *tp;
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BUSTIMESLOT *tp;
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int offset = m_busloc+ckCL+1;
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int offset = m_busloc+ckCL+1;
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tp = &m_bus[(offset+0)&(NTIMESLOTS-1)];
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tp = &m_bus[(offset+0)&(NTIMESLOTS-1)];
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printf("Setting bus timeslots from (now=%d)+%d=%d to now+%d+3\n", m_busloc, ckCL,(m_busloc+ckCL)&(NTIMESLOTS-1), ckCL);
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// printf("Setting bus timeslots from (now=%d)+%d=%d to now+%d+3\n", m_busloc, ckCL,(m_busloc+ckCL)&(NTIMESLOTS-1), ckCL);
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tp->m_addr = caddr ;
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tp->m_addr = caddr ;
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tp->m_used = 1;
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tp->m_used = 1;
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tp->m_read = 0;
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tp->m_read = 0;
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tp = &m_bus[(offset+1)&(NTIMESLOTS-1)];
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tp = &m_bus[(offset+1)&(NTIMESLOTS-1)];
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| Line 353... |
Line 350... |
}
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}
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m_busloc = (m_busloc+1)&(NTIMESLOTS-1);
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m_busloc = (m_busloc+1)&(NTIMESLOTS-1);
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BUSTIMESLOT *ts = &m_bus[m_busloc];
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BUSTIMESLOT *ts = &m_bus[m_busloc];
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if (ts->m_used) {
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printf("Current timeslot = %2d, used", m_busloc);
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if (ts->m_read)
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printf(", read");
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printf("\n");
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}
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unsigned vl = ts->m_data;
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unsigned vl = ts->m_data;
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assert( ((!ts->m_used)||(busoe))
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assert( ((!ts->m_used)||(busoe))
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|| ((ts->m_used)&&(ts->m_read)));
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|| ((ts->m_used)&&(ts->m_read)));
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assert((!ts->m_used)||(ts->m_addr < (unsigned)m_memlen));
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assert((!ts->m_used)||(ts->m_addr < (unsigned)m_memlen));
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if ((ts->m_used)&&(!ts->m_read)&&(!dm)) {
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if ((ts->m_used)&&(!ts->m_read)&&(!dm)) {
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printf("Setting MEM[%08x] = %08x\n", ts->m_addr, data);
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printf(PREFIX "::Setting MEM[%08x] = %08x\n", ts->m_addr, data);
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m_mem[ts->m_addr] = data;
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m_mem[ts->m_addr] = data;
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}
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}
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ts->m_used = 0;
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ts->m_used = 0;
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ts->m_read = 0;
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ts->m_read = 0;
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ts->m_addr = -1;
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ts->m_addr = -1;
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