URL https://opencores.org/ocsvn/wbddr3/wbddr3/trunk

Subversion Repositories wbddr3

[/] [wbddr3/] [trunk/] [bench/] [cpp/] [ddrsdramsim.h] - Diff between revs 16 and 18

Rev 16	Rev 18
Line 44...	Line 44...
`#define DDR_ACTIVATE 3`	`#define DDR_ACTIVATE 3`
`#define DDR_WRITE 4`	`#define DDR_WRITE 4`
`#define DDR_READ 5`	`#define DDR_READ 5`
`#define DDR_ZQS 6`	`#define DDR_ZQS 6`
`#define DDR_NOOP 7`	`#define DDR_NOOP 7`
	`#define DDR_DESELECT 8`

`#define NBANKS 8`	`#define NBANKS 8`
`#define NTIMESLOTS 32`	`#define NTIMESLOTS 32`
`#define NWIDTH 2`	`#define NWIDTH 1`

`class BANKINFO {`	`class BANKINFO {`
`public:`	`public:`
`int m_state;`	`int m_state;`
`unsigned m_row, m_wcounter, m_min_time_before_precharge,`	`unsigned m_row, m_wcounter, m_min_time_before_precharge,`