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https://opencores.org/ocsvn/wbddr3/wbddr3/trunk
[/] [wbddr3/] [trunk/] [bench/] [cpp/] [ddrsdramsim.h] - Diff between revs 12 and 13
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| Rev 12 |
Rev 13 |
| Line 46... |
Line 46... |
#define DDR_READ 5
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#define DDR_READ 5
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#define DDR_ZQS 6
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#define DDR_ZQS 6
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#define DDR_NOOP 7
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#define DDR_NOOP 7
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#define NBANKS 8
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#define NBANKS 8
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#define NTIMESLOTS 16
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#define NTIMESLOTS 32
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class BANKINFO {
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class BANKINFO {
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public:
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public:
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int m_state;
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int m_state;
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unsigned m_row, m_wcounter;
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unsigned m_row, m_wcounter;
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void tick(int cmd, unsigned addr=0);
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void tick(int cmd, unsigned addr=0);
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};
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};
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class BUSTIMESLOT {
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class BUSTIMESLOT {
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public:
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public:
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int m_used, m_read, m_data;
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int m_used, m_read, m_data, m_rtt;
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unsigned m_addr;
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unsigned m_addr;
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};
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};
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class DDRSDRAMSIM {
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class DDRSDRAMSIM {
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int m_reset_state, m_reset_counts, m_memlen, m_busloc,
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int m_reset_state, m_reset_counts, m_memlen, m_busloc,
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m_clocks_since_refresh, m_nrefresh_issued;
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m_clocks_since_refresh, m_nrefresh_issued,
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m_last_dqs, m_last_rtt;
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unsigned *m_mem;
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unsigned *m_mem;
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BANKINFO m_bank[8];
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BANKINFO m_bank[8];
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BUSTIMESLOT *m_bus;
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BUSTIMESLOT *m_bus;
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int cmd(int,int,int,int);
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int cmd(int,int,int,int);
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public:
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public:
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