URL https://opencores.org/ocsvn/wbddr3/wbddr3/trunk

Subversion Repositories wbddr3

[/] [wbddr3/] [trunk/] [bench/] [cpp/] [ddrsdramsim.h] - Diff between revs 13 and 14

Rev 13	Rev 14
Line 51...	Line 51...
`#define NTIMESLOTS 32`	`#define NTIMESLOTS 32`

`class BANKINFO {`	`class BANKINFO {`
`public:`	`public:`
`int m_state;`	`int m_state;`
`unsigned m_row, m_wcounter;`	`unsigned m_row, m_wcounter, m_min_time_before_precharge,`
	`m_min_time_before_activate;`
	`BANKINFO(void);`
`void tick(int cmd, unsigned addr=0);`	`void tick(int cmd, unsigned addr=0);`
`};`	`};`

`class BUSTIMESLOT {`	`class BUSTIMESLOT {`
`public:`	`public:`
Line 66...	Line 68...
`class DDRSDRAMSIM {`	`class DDRSDRAMSIM {`
`int m_reset_state, m_reset_counts, m_memlen, m_busloc,`	`int m_reset_state, m_reset_counts, m_memlen, m_busloc,`
`m_clocks_since_refresh, m_nrefresh_issued,`	`m_clocks_since_refresh, m_nrefresh_issued,`
`m_last_dqs, m_last_rtt;`	`m_last_dqs, m_last_rtt;`
`unsigned *m_mem;`	`unsigned *m_mem;`
`BANKINFO m_bank[8];`
`BUSTIMESLOT *m_bus;`	`BUSTIMESLOT *m_bus;`
`int cmd(int,int,int,int);`	`int cmd(int,int,int,int);`
`public:`	`public:`
	`BANKINFO m_bank[8];`
`DDRSDRAMSIM(int lglen);`	`DDRSDRAMSIM(int lglen);`
`unsigned operator()(int, int,`	`unsigned operator()(int, int,`
`int, int, int, int,`	`int, int, int, int,`
`int, int, int, int,`	`int, int, int, int,`
`int, int, int);`	`int, int, int);`