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https://opencores.org/ocsvn/wbddr3/wbddr3/trunk
[/] [wbddr3/] [trunk/] [bench/] [cpp/] [ddrsdramsim.h] - Diff between revs 14 and 16
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| Rev 14 |
Rev 16 |
| Line 47... |
Line 47... |
#define DDR_ZQS 6
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#define DDR_ZQS 6
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#define DDR_NOOP 7
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#define DDR_NOOP 7
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#define NBANKS 8
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#define NBANKS 8
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#define NTIMESLOTS 32
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#define NTIMESLOTS 32
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#define NWIDTH 2
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class BANKINFO {
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class BANKINFO {
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public:
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public:
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int m_state;
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int m_state;
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unsigned m_row, m_wcounter, m_min_time_before_precharge,
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unsigned m_row, m_wcounter, m_min_time_before_precharge,
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| Line 73... |
Line 74... |
BUSTIMESLOT *m_bus;
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BUSTIMESLOT *m_bus;
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int cmd(int,int,int,int);
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int cmd(int,int,int,int);
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public:
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public:
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BANKINFO m_bank[8];
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BANKINFO m_bank[8];
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DDRSDRAMSIM(int lglen);
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DDRSDRAMSIM(int lglen);
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unsigned operator()(int, int,
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unsigned apply(int, int,
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int, int, int, int,
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int, int, int, int,
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int, int, int, int,
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int, int, int, int,
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int, int, int);
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int, int, int);
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unsigned &operator[](unsigned addr) { return m_mem[addr]; };
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unsigned operator()(int reset_n, int cke,
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int csn, int rasn, int casn, int wen,
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int dqs, int dm, int odt, int busoe,
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int addr, int ba, int data) {
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return apply(reset_n, cke, csn, rasn, casn, wen, dqs, dm, odt,
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busoe, addr, ba, data);
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}
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unsigned &mem(unsigned addr) { return m_mem[addr]; };
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unsigned &operator[](unsigned addr) { return mem(addr); };
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};
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};
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#endif
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#endif
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