URL https://opencores.org/ocsvn/wbddr3/wbddr3/trunk

Subversion Repositories wbddr3

[/] [wbddr3/] [trunk/] [bench/] [cpp/] [pddrsim.h] - Diff between revs 16 and 18

Rev 16	Rev 18
Line 44...	Line 44...
`#include "ddrsdramsim.h"`	`#include "ddrsdramsim.h"`

`class PDDRSIM : protected DDRSDRAMSIM {`	`class PDDRSIM : protected DDRSDRAMSIM {`
`public:`	`public:`
`PDDRSIM(int lglen) : DDRSDRAMSIM(lglen) {};`	`PDDRSIM(int lglen) : DDRSDRAMSIM(lglen) {};`
`unsigned long operator()(int, int, int,`	`void operator()(int, int, int, unsigned, unsigned, unsigned, unsigned,`
`unsigned, unsigned, unsigned long);`	`const unsigned , unsigned );`
`unsigned long operator[](unsigned addr) {`	`unsigned operator[](unsigned addr) { return mem(addr); };`
`unsigned hdata, ldata;`	`void set(unsigned addr, unsigned data) { mem(addr) = data; };`
`unsigned long odata;`
`hdata = mem(addr<<1);`
`ldata = mem((addr<<1)+1);`

`odata = (((unsigned long)hdata)<<32)\|((unsigned long)ldata);`
`return odata; };`
`void set(unsigned addr, unsigned long data) {`
`unsigned hdata, ldata;`
`hdata = (unsigned long)(data>>32);`
`ldata = (unsigned long)(data);`

`mem((addr<<1) ) = hdata;`
`mem((addr<<1)+1) = ldata;`
`};`
`unsigned bank_state(int bankid) {`	`unsigned bank_state(int bankid) {`
`return (m_bank[bankid].m_state & 0x0ffff); };`	`return (m_bank[bankid].m_state & 0x0ffff); };`
`};`	`};`

`#endif`	`#endif`