| Line 72... |
Line 72... |
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You should have received a copy of the GNU General Public License along
|
You should have received a copy of the GNU General Public License along
|
with this program. If not, see \texttt{http://www.gnu.org/licenses/} for a copy.
|
with this program. If not, see \texttt{http://www.gnu.org/licenses/} for a copy.
|
\end{license}
|
\end{license}
|
\begin{revisionhistory}
|
\begin{revisionhistory}
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0.0 & 6/20/2016 & D. Gisselquist & Initial Version\\\hline
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0.0 & 8/02/2016 & D. Gisselquist & (Pre-release) Initial Version\\\hline
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\end{revisionhistory}
|
\end{revisionhistory}
|
% Revision History
|
% Revision History
|
% Table of Contents, named Contents
|
% Table of Contents, named Contents
|
\tableofcontents
|
\tableofcontents
|
\listoffigures
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\listoffigures
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| Line 140... |
Line 140... |
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\chapter{Architecture}
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\chapter{Architecture}
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|
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% This section describes the architecture of the block. A block level diagram
|
% This section describes the architecture of the block. A block level diagram
|
% should be included describing the top level of the design.
|
% should be included describing the top level of the design.
|
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\section{Data Structures}
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There are two basic data structures within the core: the bank data structures,
|
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and the bus data structure(s). The first keeps track of the persistent state
|
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of each bank, while the second keeps track of I/O transactions that have been
|
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initiated but not completed.
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|
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\section{Strategies}
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\section{Strategies}
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\subsection{Bank}
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\subsection{Bank}
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Currently, banks are activated (opened) when needed and only precharged
|
Currently, banks are activated (opened) when needed and only precharged
|
(closed) upon refresh request. Further, upon any read or write from one bank,
|
(closed) upon refresh request. Further, upon any read or write from one bank,
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| Line 225... |
Line 230... |
{\tt o\_wb\_data} & {\tt DAT\_O}
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{\tt o\_wb\_data} & {\tt DAT\_O}
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\end{tabular}\\\hline
|
\end{tabular}\\\hline
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\end{wishboneds}
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\end{wishboneds}
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\caption{Wishbone Datasheet}\label{tbl:wishbone}
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\caption{Wishbone Datasheet}\label{tbl:wishbone}
|
\end{center}\end{table}
|
\end{center}\end{table}
|
is required by the wishbone specification, and so
|
is required by the wishbone specification, and so it is included here. The big
|
it is included here. The big thing to notice is that all accesses to the
|
thing to notice is that all accesses to the DDR3 SDRAM memory are via 32--bit
|
DDR3 SDRAM memory are via 32--bit reads and writes to this interface. You may
|
reads and writes to this interface. You may also wish to note that the memory
|
also wish to note that the scope supports pipeline reading and writing, to
|
interface supports pipeline reading and writing, to speed up any transfers. As
|
speed up reading the results out. As a result, the memory interface speed
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a result, the memory interface speed should approach one transfer per clock
|
should approach one transfer per clock once the pipeline is loaded, although
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once the pipeline is loaded, although there will be delays loading the pipeline.
|
there will be delays loading the pipeline.
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Other than refresh cycles, once the pipeline is loaded it will continue its
|
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transfer rate at one cycle per clock for as long as it is fed at that speed.
|
|
|
Further, the Wishbone specification this core communicates with has been
|
Further, the Wishbone specification this core communicates with has been
|
simplified in this manner: The {\tt STB\_I} signal has been constrained so that
|
simplified in this manner: The {\tt STB\_I} signal has been constrained so that
|
it will only be true if {\tt CYC\_I} is also true. To interface this core
|
it will only be true if {\tt CYC\_I} is also true. To interface this core
|
in an environment without this requirement, simply create the {\tt i\_wb\_stb}
|
in an environment without this requirement, simply create the {\tt i\_wb\_stb}
|
