| Line 4... |
Line 4... |
//
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//
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// Project: OpenArty, an entirely open SoC based upon the Arty platform
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// Project: OpenArty, an entirely open SoC based upon the Arty platform
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//
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//
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// Purpose:
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// Purpose:
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//
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//
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/*
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Stall logic:
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1. First clock sets r_* variables.
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2. Second clock sets need_* variables. If need_open, need_close, or
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need_refresh are true, that should also set the o_wb_stall
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variable. Well also move r_* info to s_* (think s=stall)
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3. If stalled, the next command comes from s_*. Otherwise, from r_*.
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4. Bus FIFO fills from s_*
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//
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//
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For every transaction, one of 4 possibilities:
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1. Wait for refresh to complete
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2. Wait for precharge and activate to complete
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3. Wait for activate to complete
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4. Issue RW cmd
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5. Wait for bus transaction to complete
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6. ACK
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*/
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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| Line 95... |
Line 77... |
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_ddr_reset_n, o_ddr_cke,
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o_ddr_reset_n, o_ddr_cke,
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o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
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o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
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o_ddr_dqs, o_ddr_dm, o_ddr_odt, o_ddr_bus_oe,
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o_ddr_dqs, o_ddr_dm, o_ddr_odt, o_ddr_bus_oe,
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o_ddr_addr, o_ddr_ba, o_ddr_data, i_ddr_data,
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o_ddr_addr, o_ddr_ba, o_ddr_data, i_ddr_data);
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o_cmd_accepted);
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parameter CKREFI4 = 13'd6240, // 4 * 7.8us at 200 MHz clock
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parameter CKREFI4 = 13'd6240, // 4 * 7.8us at 200 MHz clock
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CKRFC = 320,
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CKRFC = 320,
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CKXPR = CKRFC+5+2; // Clocks per tXPR timeout
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CKXPR = CKRFC+5+2; // Clocks per tXPR timeout
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input i_clk, i_reset;
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input i_clk, i_reset;
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// Wishbone inputs
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// Wishbone inputs
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| Line 122... |
Line 103... |
output reg [13:0] o_ddr_addr;
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output reg [13:0] o_ddr_addr;
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output reg [2:0] o_ddr_ba;
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output reg [2:0] o_ddr_ba;
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// And the data inputs and outputs
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// And the data inputs and outputs
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output reg [31:0] o_ddr_data;
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output reg [31:0] o_ddr_data;
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input [31:0] i_ddr_data;
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input [31:0] i_ddr_data;
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// And just for the test bench
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output reg o_cmd_accepted;
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always @(posedge i_clk)
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o_cmd_accepted <= (i_wb_stb)&&(~o_wb_stall);
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reg drive_dqs;
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reg drive_dqs;
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// The pending transaction
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// The pending transaction
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reg [31:0] r_data;
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reg [31:0] r_data;
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| Line 144... |
Line 120... |
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// The pending transaction, one further into the pipeline. This is
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// The pending transaction, one further into the pipeline. This is
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// the stage where the read/write command is actually given to the
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// the stage where the read/write command is actually given to the
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// interface if we haven't stalled.
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// interface if we haven't stalled.
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reg [31:0] s_data;
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reg [31:0] s_data;
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reg s_pending, s_we, s_match;
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reg s_pending, s_we; // , s_match;
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reg [25:0] s_addr;
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reg [25:0] s_addr;
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reg [13:0] s_row, s_nxt_row;
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reg [13:0] s_row, s_nxt_row;
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reg [2:0] s_bank, s_nxt_bank;
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reg [2:0] s_bank, s_nxt_bank;
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reg [9:0] s_col;
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reg [9:0] s_col;
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reg [1:0] s_sub;
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reg [1:0] s_sub;
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| Line 628... |
Line 604... |
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// pre-emptive work
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// pre-emptive work
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s_nxt_row <= r_nxt_row;
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s_nxt_row <= r_nxt_row;
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s_nxt_bank <= r_nxt_bank;
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s_nxt_bank <= r_nxt_bank;
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s_match <= w_s_match;
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// s_match <= w_s_match;
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end
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end
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end
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end
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wire w_need_close_this_bank, w_need_open_bank,
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wire w_need_close_this_bank, w_need_open_bank,
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w_r_valid, w_s_valid;
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w_r_valid, w_s_valid;
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| Line 652... |
Line 628... |
&&(!bus_active[0]);
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&&(!bus_active[0]);
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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need_close_bank <= (w_need_close_this_bank)
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need_close_bank <= (w_need_close_this_bank)
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&&(!need_open_bank)
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&&(!need_close_bank)
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&&(!w_this_closing_bank)&&(!last_closing_bank);
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&&(!w_this_closing_bank)&&(!last_closing_bank);
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maybe_close_next_bank <= (r_pending)
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maybe_close_next_bank <= (r_pending)
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&&(bank_status[r_nxt_bank][0])
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&&(bank_status[r_nxt_bank][0])
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&&(r_nxt_row != bank_address[r_nxt_bank])
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&&(r_nxt_row != bank_address[r_nxt_bank])
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| Line 805... |
Line 783... |
begin
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begin
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bus_fifo_head <= 4'h0;
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bus_fifo_head <= 4'h0;
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bus_fifo_tail <= 4'h0;
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bus_fifo_tail <= 4'h0;
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o_ddr_dm <= 1'b0;
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o_ddr_dm <= 1'b0;
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end else begin
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end else begin
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if ((w_this_rw_move)||((s_pending)&&(s_match)&&(!pipe_stall)))
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if
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//((w_this_rw_move)||((s_pending)&&(s_match)&&(!pipe_stall)))
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((s_pending)&&(!pipe_stall))
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bus_fifo_head <= bus_fifo_head + 4'h1;
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bus_fifo_head <= bus_fifo_head + 4'h1;
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o_ddr_dm <= (bus_active[`BUSREG])&&(!bus_read[`BUSREG]);
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o_ddr_dm <= (bus_active[`BUSREG])&&(!bus_read[`BUSREG]);
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if (w_bus_fifo_read_next_transaction)
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if (w_bus_fifo_read_next_transaction)
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begin
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begin
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