| Line 91... |
Line 91... |
// Wishbone outputs
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// Wishbone outputs
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output reg o_wb_ack;
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output reg o_wb_ack;
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output reg o_wb_stall;
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output reg o_wb_stall;
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output reg [31:0] o_wb_data;
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output reg [31:0] o_wb_data;
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// DDR3 RAM Controller
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// DDR3 RAM Controller
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output wire o_ddr_reset_n, o_ddr_cke;
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output reg o_ddr_reset_n, o_ddr_cke;
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// Control outputs
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// Control outputs
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output reg o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n,o_ddr_we_n;
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output wire o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n,o_ddr_we_n;
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// DQS outputs:set to 3'b010 when data is active, 3'b100 (i.e. 2'bzz) ow
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// DQS outputs:set to 3'b010 when data is active, 3'b100 (i.e. 2'bzz) ow
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output wire o_ddr_dqs;
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output wire o_ddr_dqs;
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output reg o_ddr_dm, o_ddr_odt, o_ddr_bus_oe;
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output reg o_ddr_dm;
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output wire o_ddr_odt, o_ddr_bus_oe;
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// Address outputs
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// Address outputs
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output reg [13:0] o_ddr_addr;
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output wire [13:0] o_ddr_addr;
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output reg [2:0] o_ddr_ba;
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output wire [2:0] o_ddr_ba;
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// And the data inputs and outputs
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// And the data inputs and outputs
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output reg [31:0] o_ddr_data;
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output reg [31:0] o_ddr_data;
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input [31:0] i_ddr_data;
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input [31:0] i_ddr_data;
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reg drive_dqs;
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reg drive_dqs;
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| Line 212... |
Line 213... |
begin
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begin
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if (reset_instruction[`DDR_RSTDONE])
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if (reset_instruction[`DDR_RSTDONE])
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reset_override <= 1'b0;
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reset_override <= 1'b0;
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reset_cmd <= reset_instruction[20:0];
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reset_cmd <= reset_instruction[20:0];
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end
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end
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always @(posedge i_clk)
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if (i_reset)
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o_ddr_cke <= 1'b0;
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else if ((reset_override)&&(reset_ztimer))
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o_ddr_cke <= reset_instruction[`DDR_CKEBIT];
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initial reset_ztimer = 1'b0; // Is the timer zero?
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initial reset_ztimer = 1'b0; // Is the timer zero?
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initial reset_timer = 17'h02;
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initial reset_timer = 17'h02;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_reset)
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if (i_reset)
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| Line 471... |
Line 467... |
assign w_ckREFRst[12: 0] = CKRFC-2-12;
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assign w_ckREFRst[12: 0] = CKRFC-2-12;
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assign w_ckREFRst[16:13] = 4'h0;
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assign w_ckREFRst[16:13] = 4'h0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (reset_override)
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if (reset_override)
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refresh_instruction <= { 3'h0, `DDR_NOOP, w_ckREFIn };
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refresh_cmd <= { 3'h0, `DDR_NOOP, w_ckREFIn };
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else if (refresh_ztimer)
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else if (refresh_ztimer)
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refresh_cmd <= refresh_instruction[20:0];
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refresh_cmd <= refresh_instruction[20:0];
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (reset_override)
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if (reset_override)
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need_refresh <= 1'b0;
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need_refresh <= 1'b0;
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| Line 649... |
Line 645... |
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maybe_open_next_bank <= (r_pending)
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maybe_open_next_bank <= (r_pending)
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&&(bank_status[r_bank][0] == 1'b1)
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&&(bank_status[r_bank][0] == 1'b1)
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&&(bank_status[r_nxt_bank][1:0] == 2'b00)
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&&(bank_status[r_nxt_bank][1:0] == 2'b00)
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&&(!w_this_maybe_open)&&(!last_maybe_open);
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&&(!w_this_maybe_open)&&(!last_maybe_open);
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last_maybe_open <= (w_this_maybe_open);
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activate_bank_cmd<= { `DDR_ACTIVATE, r_bank, r_row[13:0] };
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activate_bank_cmd<= { `DDR_ACTIVATE, r_bank, r_row[13:0] };
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maybe_open_cmd <= { `DDR_ACTIVATE,r_nxt_bank, r_nxt_row[13:0] };
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maybe_open_cmd <= { `DDR_ACTIVATE,r_nxt_bank, r_nxt_row[13:0] };
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