| Line 80... |
Line 80... |
o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
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o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
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o_ddr_dqs, o_ddr_dm, o_ddr_odt, o_ddr_bus_oe,
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o_ddr_dqs, o_ddr_dm, o_ddr_odt, o_ddr_bus_oe,
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o_ddr_addr, o_ddr_ba, o_ddr_data, i_ddr_data);
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o_ddr_addr, o_ddr_ba, o_ddr_data, i_ddr_data);
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parameter CKREFI4 = 13'd6240, // 4 * 7.8us at 200 MHz clock
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parameter CKREFI4 = 13'd6240, // 4 * 7.8us at 200 MHz clock
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CKRFC = 320,
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CKRFC = 320,
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CKWR = 3,
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CKXPR = CKRFC+5+2; // Clocks per tXPR timeout
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CKXPR = CKRFC+5+2; // Clocks per tXPR timeout
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input i_clk, i_reset;
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input i_clk, i_reset;
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// Wishbone inputs
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// Wishbone inputs
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input i_wb_cyc, i_wb_stb, i_wb_we;
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input [25:0] i_wb_addr;
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input [25:0] i_wb_addr;
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| Line 156... |
Line 157... |
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wire w_this_closing_bank, w_this_opening_bank,
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wire w_this_closing_bank, w_this_opening_bank,
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w_this_maybe_close, w_this_maybe_open,
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w_this_maybe_close, w_this_maybe_open,
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w_this_rw_move;
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w_this_rw_move;
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reg last_closing_bank, last_opening_bank;
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reg last_closing_bank, last_opening_bank;
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wire w_need_close_this_bank, w_need_open_bank,
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w_r_valid, w_s_valid;
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//
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//
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// tWTR = 7.5
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// tWTR = 7.5
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// tRRD = 7.5
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// tRRD = 7.5
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// tREFI= 7.8
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// tREFI= 7.8
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// tFAW = 45
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// tFAW = 45
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| Line 338... |
Line 341... |
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wire w_precharge_all;
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wire w_precharge_all;
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reg banks_are_closing, all_banks_closed;
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reg banks_are_closing, all_banks_closed;
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reg [3:0] bank_status [0:7];
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reg [3:0] bank_status [0:7];
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reg [13:0] bank_address [0:7];
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reg [13:0] bank_address [0:7];
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reg [3:0] bank_wr_ck [0:7]; // tWTR
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reg bank_wr_ckzro [0:7]; // tWTR
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wire [3:0] write_recycle_clocks;
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assign write_recycle_clocks = CKWR+4+4;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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bank_status[0] <= { bank_status[0][2:0], bank_status[0][0] };
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bank_status[0] <= { bank_status[0][2:0], bank_status[0][0] };
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bank_status[1] <= { bank_status[1][2:0], bank_status[1][0] };
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bank_status[1] <= { bank_status[1][2:0], bank_status[1][0] };
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| Line 357... |
Line 365... |
&&(bank_status[3][2:0] == 3'b00)
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&&(bank_status[3][2:0] == 3'b00)
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&&(bank_status[4][2:0] == 3'b00)
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&&(bank_status[4][2:0] == 3'b00)
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&&(bank_status[5][2:0] == 3'b00)
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&&(bank_status[5][2:0] == 3'b00)
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&&(bank_status[6][2:0] == 3'b00)
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&&(bank_status[6][2:0] == 3'b00)
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&&(bank_status[7][2:0] == 3'b00);
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&&(bank_status[7][2:0] == 3'b00);
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bank_wr_ck[0] <= (|bank_wr_ck[0])?(bank_wr_ck[0]-4'h1):4'h0;
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bank_wr_ck[1] <= (|bank_wr_ck[1])?(bank_wr_ck[1]-4'h1):4'h0;
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bank_wr_ck[2] <= (|bank_wr_ck[2])?(bank_wr_ck[2]-4'h1):4'h0;
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bank_wr_ck[3] <= (|bank_wr_ck[3])?(bank_wr_ck[3]-4'h1):4'h0;
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bank_wr_ck[4] <= (|bank_wr_ck[4])?(bank_wr_ck[4]-4'h1):4'h0;
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bank_wr_ck[5] <= (|bank_wr_ck[5])?(bank_wr_ck[5]-4'h1):4'h0;
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bank_wr_ck[6] <= (|bank_wr_ck[6])?(bank_wr_ck[6]-4'h1):4'h0;
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bank_wr_ck[7] <= (|bank_wr_ck[7])?(bank_wr_ck[7]-4'h1):4'h0;
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bank_wr_ckzro[0] <= (bank_wr_ck[0][3:1]==3'b00);
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bank_wr_ckzro[1] <= (bank_wr_ck[1][3:1]==3'b00);
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bank_wr_ckzro[2] <= (bank_wr_ck[2][3:1]==3'b00);
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bank_wr_ckzro[3] <= (bank_wr_ck[3][3:1]==3'b00);
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bank_wr_ckzro[4] <= (bank_wr_ck[4][3:1]==3'b00);
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bank_wr_ckzro[5] <= (bank_wr_ck[5][3:1]==3'b00);
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bank_wr_ckzro[6] <= (bank_wr_ck[6][3:1]==3'b00);
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bank_wr_ckzro[7] <= (bank_wr_ck[7][3:1]==3'b00);
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|
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if (w_this_rw_move)
|
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bank_wr_ck[rw_cmd[16:14]] <= (rw_cmd[`DDR_WEBIT])? 4'h0
|
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: write_recycle_clocks;
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|
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if (reset_override)
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if (reset_override)
|
begin
|
begin
|
bank_status[0][0] <= 1'b0;
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bank_status[0][0] <= 1'b0;
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bank_status[1][0] <= 1'b0;
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bank_status[1][0] <= 1'b0;
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bank_status[2][0] <= 1'b0;
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bank_status[2][0] <= 1'b0;
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| Line 467... |
Line 498... |
assign w_ckREFRst[12: 0] = CKRFC-2-12;
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assign w_ckREFRst[12: 0] = CKRFC-2-12;
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assign w_ckREFRst[16:13] = 4'h0;
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assign w_ckREFRst[16:13] = 4'h0;
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|
|
always @(posedge i_clk)
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always @(posedge i_clk)
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if (reset_override)
|
if (reset_override)
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refresh_cmd <= { 3'h0, `DDR_NOOP, w_ckREFIn };
|
refresh_cmd <= { `DDR_NOOP, w_ckREFIn };
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else if (refresh_ztimer)
|
else if (refresh_ztimer)
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refresh_cmd <= refresh_instruction[20:0];
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refresh_cmd <= refresh_instruction[20:0];
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (reset_override)
|
if (reset_override)
|
need_refresh <= 1'b0;
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need_refresh <= 1'b0;
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| Line 604... |
Line 635... |
|
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// s_match <= w_s_match;
|
// s_match <= w_s_match;
|
end
|
end
|
end
|
end
|
|
|
wire w_need_close_this_bank, w_need_open_bank,
|
|
w_r_valid, w_s_valid;
|
|
assign w_need_close_this_bank = (r_pending)&&(bank_status[r_bank][0])
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assign w_need_close_this_bank = (r_pending)&&(bank_status[r_bank][0])
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&&(bank_wr_ckzro[r_bank])
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&&(r_row != bank_address[r_bank])
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&&(r_row != bank_address[r_bank])
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||(pipe_stall)&&(s_pending)&&(bank_status[s_bank][0])
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||(pipe_stall)&&(s_pending)&&(bank_status[s_bank][0])
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&&(s_row != bank_address[s_bank]);
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&&(s_row != bank_address[s_bank]);
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assign w_need_open_bank = (r_pending)&&(bank_status[r_bank][1:0]==2'b00)
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assign w_need_open_bank = (r_pending)&&(bank_status[r_bank][1:0]==2'b00)
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||(pipe_stall)&&(s_pending)&&(bank_status[s_bank][1:0]==2'b00);
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||(pipe_stall)&&(s_pending)&&(bank_status[s_bank][1:0]==2'b00);
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assign w_r_valid = (!need_refresh)&&(r_pending)
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assign w_r_valid = (!need_refresh)&&(r_pending)
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&&(bank_status[r_bank][3])
|
&&(bank_status[r_bank][3])
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&&(bank_address[r_bank]==r_row)
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&&(bank_address[r_bank]==r_row)
|
|
&&((r_we)||(bank_wr_ckzro[r_bank]))
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&&(!bus_active[0]);
|
&&(!bus_active[0]);
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assign w_s_valid = (!need_refresh)&&(s_pending)
|
assign w_s_valid = (!need_refresh)&&(s_pending)
|
&&(bank_status[s_bank][3])
|
&&(bank_status[s_bank][3])
|
&&(bank_address[s_bank]==s_row)
|
&&(bank_address[s_bank]==s_row)
|
|
&&((r_we)||(bank_wr_ckzro[s_bank]))
|
&&(!bus_active[0]);
|
&&(!bus_active[0]);
|
|
|
always @(posedge i_clk)
|
always @(posedge i_clk)
|
begin
|
begin
|
need_close_bank <= (w_need_close_this_bank)
|
need_close_bank <= (w_need_close_this_bank)
|
| Line 630... |
Line 662... |
&&(!need_close_bank)
|
&&(!need_close_bank)
|
&&(!w_this_closing_bank)&&(!last_closing_bank);
|
&&(!w_this_closing_bank)&&(!last_closing_bank);
|
|
|
maybe_close_next_bank <= (r_pending)
|
maybe_close_next_bank <= (r_pending)
|
&&(bank_status[r_nxt_bank][0])
|
&&(bank_status[r_nxt_bank][0])
|
|
&&(bank_wr_ckzro[r_nxt_bank])
|
&&(r_nxt_row != bank_address[r_nxt_bank])
|
&&(r_nxt_row != bank_address[r_nxt_bank])
|
&&(!w_this_maybe_close)&&(!last_maybe_close);
|
&&(!w_this_maybe_close)&&(!last_maybe_close);
|
|
|
close_bank_cmd <= { `DDR_PRECHARGE, r_bank, r_row[13:11], 1'b0, r_row[9:0] };
|
close_bank_cmd <= { `DDR_PRECHARGE, r_bank, r_row[13:11], 1'b0, r_row[9:0] };
|
maybe_close_cmd <= { `DDR_PRECHARGE, r_nxt_bank, r_nxt_row[13:11], 1'b0, r_nxt_row[9:0] };
|
maybe_close_cmd <= { `DDR_PRECHARGE, r_nxt_bank, r_nxt_row[13:11], 1'b0, r_nxt_row[9:0] };
|
