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https://opencores.org/ocsvn/wbddr3/wbddr3/trunk
[/] [wbddr3/] [trunk/] [rtl/] [wbddrsdram.v] - Diff between revs 16 and 17
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Rev 16 |
Rev 17 |
Line 82... |
Line 82... |
// Wishbone inputs
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// Wishbone inputs
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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i_wb_sel,
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i_wb_sel,
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// Wishbone outputs
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// Wishbone outputs
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o_wb_ack, o_wb_stall, o_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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// Memory command wires
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o_ddr_reset_n, o_ddr_cke, o_ddr_bus_oe,
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o_ddr_reset_n, o_ddr_cke, o_ddr_bus_oe,
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o_ddr_cmd_a, o_ddr_cmd_b,
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o_ddr_cmd_a, o_ddr_cmd_b,
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// And the data wires to go with them ....
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o_ddr_data, i_ddr_data);
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o_ddr_data, i_ddr_data);
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// These parameters are not really meant for adjusting from the
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// These parameters are not really meant for adjusting from the
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// top level. These are more internal variables, recorded here
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// top level. These are more internal variables, recorded here
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// so that things can be automatically adjusted without much
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// so that things can be automatically adjusted without much
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// problem.
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// problem.
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