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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: dragonball_wbmaster.v,v 1.1.1.1 2002-12-03 09:02:31 rherveille Exp $
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// $Id: dragonball_wbmaster.v,v 1.2 2002-12-22 16:09:33 rherveille Exp $
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//
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//
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// $Date: 2002-12-03 09:02:31 $
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// $Date: 2002-12-22 16:09:33 $
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// $Revision: 1.1.1.1 $
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// $Revision: 1.2 $
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// $Author: rherveille $
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// $Author: rherveille $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// $Log: not supported by cvs2svn $
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//
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//
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//
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// This core converts a 16bit DragonBall bus interface into a 16bit
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// This core converts a 16bit DragonBall bus interface into a 16bit
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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module dragonix_wbmaster(
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module dragonball_wbmaster(
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clk, reset_n,
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clk, reset_n,
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a, cs_n, d, lwe_n, uwe_n, oe_n, dtack_n, berr,
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a, cs_n, d, lwe_n, uwe_n, oe_n, dtack_n, berr,
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clk_o, rst_o, cyc_o, stb_o, adr_o, sel_o, we_o, dat_o, dat_i, ack_i, err_i
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clk_o, rst_o, cyc_o, stb_o, adr_o, sel_o, we_o, dat_o, dat_i, ack_i, err_i
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);
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);
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reg cyc_o, stb_o;
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reg cyc_o, stb_o;
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reg [adr_hi:1] adr_o;
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reg [adr_hi:1] adr_o;
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reg [ 1:0] sel_o;
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reg [ 1:0] sel_o;
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reg we_o;
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reg we_o;
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reg [ 15:0] dat_o;
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reg dtack;
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reg dtack;
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reg [ 15:0] sdat_i;
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wire cs = !cs_n & !(ack_i | err_i | dtack); // generate active high chip select signal
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wire cs = !cs_n & !(ack_i | err_i | dtack); // generate active high chip select signal
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wire lwe = !lwe_n; // generate active high lo_write_enable signal
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wire lwe = !lwe_n; // generate active high lo_write_enable signal
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wire uwe = !uwe_n; // generate active high hi_write_enable signal
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wire uwe = !uwe_n; // generate active high hi_write_enable signal
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wire oe = !oe_n; // generate active high output enable signal
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wire oe = !oe_n; // generate active high output enable signal
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cyc_o <= #1 1'b0;
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cyc_o <= #1 1'b0;
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stb_o <= #1 1'b0;
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stb_o <= #1 1'b0;
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adr_o <= #1 {{adr_hi-1}{1'b0}};
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adr_o <= #1 {{adr_hi-1}{1'b0}};
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sel_o <= #1 2'b00;
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sel_o <= #1 2'b00;
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we_o <= #1 1'b0;
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we_o <= #1 1'b0;
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dat_o <= #1 16'h0;
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dtack <= #1 1'b0;
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dtack <= #1 1'b0;
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sdat_i <= #1 16'h0;
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end
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end
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else
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else
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begin
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begin
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cyc_o <= #1 cs; // assert cyc_o when CS asserted
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cyc_o <= #1 cs; // assert cyc_o when CS asserted
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stb_o <= #1 cs; // assert stb_o when CS asserted
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stb_o <= #1 cs; // assert stb_o when CS asserted
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adr_o <= #1 a; // address == external address
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adr_o <= #1 a; // address == external address
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sel_o <= #1 oe ? 2'b11 : {uwe, lwe}; // generate select lines;
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sel_o <= #1 oe ? 2'b11 : {uwe, lwe}; // generate select lines;
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// read (oe asserted): SEL[1:0] = '11'
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// read (oe asserted): SEL[1:0] = '11'
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// write (oe negated): SEL[1:0] = 'uwe, lwe'
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// write (oe negated): SEL[1:0] = 'uwe, lwe'
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we_o <= #1 uwe | lwe; // write == uwe OR lwe asserted
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we_o <= #1 uwe | lwe; // write == uwe OR lwe asserted
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dat_o <= #1 d; // dat_o == external data
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dtack <= ack_i & !dtack; // generate DTACK signal
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dtack <= #1 ack_i & !dtack; // generate DTACK signal
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sdat_i <= #1 dat_i; // synchronize dat_i
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end
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end
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assign d = (cs & oe) ? dat_i : 16'hzzzz; // generate databus tri-state buffers
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assign dat_o = d; // dat_o==external databus (not synchronised!!)
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assign d = (~cs_n & oe) ? sdat_i : 16'hzzzz; // generate databus tri-state buffers
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assign dtack_n = !dtack; // generate active low DTACK signal
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assign dtack_n = !dtack; // generate active low DTACK signal
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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