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https://opencores.org/ocsvn/wbscope/wbscope/trunk
[/] [wbscope/] [trunk/] [rtl/] [wbscope.v] - Diff between revs 9 and 10
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| Rev 9 |
Rev 10 |
| Line 294... |
Line 294... |
end
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end
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reg [31:0] nxt_mem;
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reg [31:0] nxt_mem;
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always @(posedge i_wb_clk)
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always @(posedge i_wb_clk)
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nxt_mem <= mem[raddr+waddr+
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nxt_mem <= mem[raddr+waddr+
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((bw_cyc_stb)&&(i_wb_addr)&&(~i_wb_we))];
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(((bw_cyc_stb)&&(i_wb_addr)&&(~i_wb_we)) ?
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{{(LGMEM-1){1'b0}},1'b1} : { (LGMEM){1'b0}} )];
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wire [4:0] bw_lgmem;
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wire [4:0] bw_lgmem;
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assign bw_lgmem = LGMEM;
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assign bw_lgmem = LGMEM;
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always @(posedge i_wb_clk)
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always @(posedge i_wb_clk)
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if (~i_wb_addr) // Control register read
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if (~i_wb_addr) // Control register read
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