| Line 201... |
Line 201... |
end else if ((i_ce)&&(dr_triggered))
|
end else if ((i_ce)&&(dr_triggered))
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begin // MUST BE a < and not <=, so that we can keep this w/in
|
begin // MUST BE a < and not <=, so that we can keep this w/in
|
// 20 bits. Else we'd need to add a bit to comparison
|
// 20 bits. Else we'd need to add a bit to comparison
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// here.
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// here.
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if (counter < bw_holdoff)
|
if (counter < bw_holdoff)
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counter <= counter + 1;
|
counter <= counter + 20'h01;
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else
|
else
|
dr_stopped <= 1'b1;
|
dr_stopped <= 1'b1;
|
end
|
end
|
|
|
//
|
//
|
| Line 226... |
Line 226... |
begin
|
begin
|
waddr <= 0; // upon reset.
|
waddr <= 0; // upon reset.
|
dr_primed <= 1'b0;
|
dr_primed <= 1'b0;
|
end else if ((i_ce)&&((~dr_triggered)||(counter < bw_holdoff)))
|
end else if ((i_ce)&&((~dr_triggered)||(counter < bw_holdoff)))
|
begin
|
begin
|
mem[waddr] <= i_data;
|
// mem[waddr] <= i_data;
|
waddr <= waddr + 1;
|
waddr <= waddr + {{(LGMEM-1){1'b0}},1'b1};
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dr_primed <= (dr_primed)||(&waddr);
|
dr_primed <= (dr_primed)||(&waddr);
|
end
|
end
|
|
always @(posedge i_clk)
|
|
if ((i_ce)&&((~dr_triggered)||(counter < bw_holdoff)))
|
|
mem[waddr] <= i_data;
|
|
|
//
|
//
|
// Clock transfer of the status signals
|
// Clock transfer of the status signals
|
//
|
//
|
wire bw_stopped, bw_triggered, bw_primed;
|
wire bw_stopped, bw_triggered, bw_primed;
|
| Line 276... |
Line 279... |
begin
|
begin
|
if ((bw_reset_request)
|
if ((bw_reset_request)
|
||((bw_cyc_stb)&&(i_wb_addr)&&(i_wb_we)))
|
||((bw_cyc_stb)&&(i_wb_addr)&&(i_wb_we)))
|
raddr <= 0;
|
raddr <= 0;
|
else if ((bw_cyc_stb)&&(i_wb_addr)&&(~i_wb_we)&&(bw_stopped))
|
else if ((bw_cyc_stb)&&(i_wb_addr)&&(~i_wb_we)&&(bw_stopped))
|
raddr <= raddr + 1; // Data read, when stopped
|
raddr <= raddr + {{(LGMEM-1){1'b0}},1'b1}; // Data read, when stopped
|
|
|
if ((bw_cyc_stb)&&(~i_wb_we))
|
if ((bw_cyc_stb)&&(~i_wb_we))
|
begin // Read from the bus
|
begin // Read from the bus
|
br_wb_ack <= 1'b1;
|
br_wb_ack <= 1'b1;
|
end else if ((bw_cyc_stb)&&(i_wb_we))
|
end else if ((bw_cyc_stb)&&(i_wb_we))
|
| Line 288... |
Line 291... |
br_wb_ack <= 1'b1;
|
br_wb_ack <= 1'b1;
|
else // Do nothing if either i_wb_cyc or i_wb_stb are low
|
else // Do nothing if either i_wb_cyc or i_wb_stb are low
|
br_wb_ack <= 1'b0;
|
br_wb_ack <= 1'b0;
|
end
|
end
|
|
|
|
reg [31:0] nxt_mem;
|
|
always @(posedge i_wb_clk)
|
|
nxt_mem <= mem[raddr+waddr+
|
|
((bw_cyc_stb)&&(i_wb_addr)&&(~i_wb_we))];
|
|
|
wire [4:0] bw_lgmem;
|
wire [4:0] bw_lgmem;
|
assign bw_lgmem = LGMEM;
|
assign bw_lgmem = LGMEM;
|
always @(posedge i_wb_clk)
|
always @(posedge i_wb_clk)
|
if (~i_wb_addr) // Control register read
|
if (~i_wb_addr) // Control register read
|
o_wb_data <= { bw_reset_request,
|
o_wb_data <= { bw_reset_request,
|
| Line 304... |
Line 312... |
bw_lgmem,
|
bw_lgmem,
|
bw_holdoff };
|
bw_holdoff };
|
else if (~bw_stopped) // read, prior to stopping
|
else if (~bw_stopped) // read, prior to stopping
|
o_wb_data <= i_data;
|
o_wb_data <= i_data;
|
else // if (i_wb_addr) // Read from FIFO memory
|
else // if (i_wb_addr) // Read from FIFO memory
|
o_wb_data <= mem[raddr+waddr];
|
o_wb_data <= nxt_mem; // mem[raddr+waddr];
|
|
|
assign o_wb_stall = 1'b0;
|
assign o_wb_stall = 1'b0;
|
assign o_wb_ack = (i_wb_cyc)&&(br_wb_ack);
|
assign o_wb_ack = (i_wb_cyc)&&(br_wb_ack);
|
|
|
reg br_level_interrupt;
|
reg br_level_interrupt;
|
