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##
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##
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## Filename: Makefile
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## Filename: Makefile
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##
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##
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## Project: wbuart32, a full featured UART with simulator
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## Project: wbuart32, a full featured UART with simulator
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##
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##
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## Purpose:
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## Purpose: To test a group of Verilator modules: txuart (UART transmitter),
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## rxuart (UART receiver/sink) and wbuart (UART module, containing
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## both receiver and transmitter, with FIFOs, controlled via wishbone).
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##
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##
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## Targets:
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## test
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## Perform both tests. The end result should be either a PASS
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## or a FAIL.
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##
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## helloworld
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## A non-automated, and less interactive test than the others. In
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## this test, the UART simply produces a Hello World message to the
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## screen over and over again.
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##
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## linetest
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## An automated test of both txuart and rxuart. The test works
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## by sending a message through the rxuart, and receiving the
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## message via the txuart. This depends upon a Verilog test
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## infrastructure, linetest.v.
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##
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## This test may be ran in an interactive mode. In this mode,
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## characters written to the UART will be reflected back upon
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## the entrance of a return character.
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##
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## speechtest
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## An automated test of the wbuart, txuart, and fifo. In this
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## case, the test RTL produces a copy of the Gettysburg address,
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## filling the FIFO at 12/16 at a time. In automated mode, the
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## speechtest will compare the output against against a text copy
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## of the speech, and report upon any success or failure.
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##
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## In interactive mode, the test will repeatedly print out the
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## Gettysburg address until stopped. (It may take a significant
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## amount of time between copies of the Gettysburg address ...)
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##
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##
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##
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## Creator: Dan Gisselquist, Ph.D.
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## Creator: Dan Gisselquist, Ph.D.
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## Gisselquist Technology, LLC
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## Gisselquist Technology, LLC
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##
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##
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################################################################################
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################################################################################
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##
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##
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CXX := g++
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CXX := g++
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FLAGS := -Wall -Og -g
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FLAGS := -Wall -Og -g
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OBJDIR := obj-pc
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OBJDIR := obj-pc
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RTLD := ../verilog
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RTLD := ../verilog
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VERILATOR_ROOT ?= $(shell bash -c 'verilator -V|grep VERILATOR_ROOT | head -1 | sed -e " s/^.*=\s*//"')
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VROOT := $(VERILATOR_ROOT)
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INCS := -I$(RTLD)/obj_dir/ -I/usr/share/verilator/include
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INCS := -I$(RTLD)/obj_dir/ -I/usr/share/verilator/include
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SOURCES := linetest.cpp
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SOURCES := helloworld.cpp linetest.cpp uartsim.cpp uartsim.h
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VOBJDR := $(RTLD)/obj_dir
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VOBJDR := $(RTLD)/obj_dir
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VLIB := /usr/share/verilator/include/verilated.cpp
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SYSVDR := /usr/share/verilator/include
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SIMSRCS := linetest.cpp uartsim.cpp
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VLIB := $(SYSVDR)/verilated.cpp $(SYSVDR)/verilated_vcd_c.cpp
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SIMOBJ := $(subst .cpp,.o,$(SIMSRCS))
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# Sources necessary to build the linetest program (rxuart-txuart test)
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SIMOBJS:= $(addprefix $(OBJDIR)/,$(SIMOBJ))
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LINSRCS := linetest.cpp uartsim.cpp
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all: $(OBJDIR)/ linetest
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LINOBJ := $(subst .cpp,.o,$(LINSRCS))
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LINOBJS:= $(addprefix $(OBJDIR)/,$(LINOBJ))
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# Sources necessary to build the helloworld test (txuart test)
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HLOSRCS := helloworld.cpp uartsim.cpp
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HLOOBJ := $(subst .cpp,.o,$(HLOSRCS))
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HLOOBJS:= $(addprefix $(OBJDIR)/,$(HLOOBJ))
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# Sources necessary to build the speech test (wbuart test)
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SPCHSRCS:= speechtest.cpp uartsim.cpp
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SPCHOBJ := $(subst .cpp,.o,$(SPCHSRCS))
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SPCHOBJS:= $(addprefix $(OBJDIR)/,$(SPCHOBJ))
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all: $(OBJDIR)/ linetest helloworld speechtest test
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$(OBJDIR)/:
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$(OBJDIR)/:
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@bash -c "if [ ! -e $(OBJDIR) ]; then mkdir -p $(OBJDIR); fi"
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@bash -c "if [ ! -e $(OBJDIR) ]; then mkdir -p $(OBJDIR); fi"
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$(OBJDIR)/uartsim.o: uartsim.cpp uartsim.h
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$(OBJDIR)/uartsim.o: uartsim.cpp uartsim.h
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$(OBJDIR)/%.o: %.cpp
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$(OBJDIR)/%.o: %.cpp
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$(CXX) $(FLAGS) $(INCS) -c $< -o $@
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$(CXX) $(FLAGS) $(INCS) -c $< -o $@
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linetest: $(OBJDIR)/linetest.o $(OBJDIR)/uartsim.o $(VOBJDR)/Vlinetest__ALL.a
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linetest: $(LINOBJS) $(VOBJDR)/Vlinetest__ALL.a
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$(CXX) $(FLAGS) $(INCS) $^ $(VLIB) -o $@
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helloworld: $(HLOOBJS) $(VOBJDR)/Vhelloworld__ALL.a
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$(CXX) $(FLAGS) $(INCS) $^ $(VLIB) -o $@
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$(CXX) $(FLAGS) $(INCS) $^ $(VLIB) -o $@
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#
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# The speech test program depends upon a copy of the Gettysburg Address,
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# turned into a hex file format which will be read by the Verilog/RTL
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# $readmemh function. However, we need to create that hex file that will
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# written. That's the purpose of mkspeech--to make a file that can be read
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# by $readmemh.
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#
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mkspeech: mkspeech.cpp
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$(CXX) mkspeech.cpp -o $@
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# Now that mkspeech is available, use it to produce a speech.hex file from
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# the speech.txt file. Be careful if you adjust this speech: the speechfifo.v
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# verilog file depends upon the exact number of characters--its not a portable
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# dependency, but ... it is what it is.
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speech.hex: mkspeech speech.txt
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./mkspeech speech.txt
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# Now, if the speech.hex file is available, then we can perform our final build.
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# Actually, we could've done this without the speech file being available, but
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# this works.
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speechtest: speech.hex $(SPCHOBJS) $(VOBJDR)/Vspeechfifo__ALL.a
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$(CXX) $(FLAGS) $(INCS) $(SPCHOBJS) $(VOBJDR)/Vspeechfifo__ALL.a $(VLIB) -o $@
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test: linetest speechtest
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./linetest
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./speechtest
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.PHONY: clean
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.PHONY: clean
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clean:
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clean:
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rm -f ./linetest
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rm -f ./linetest ./helloworld ./speechtest
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rm -f ./mkspeech ./speech.hex
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rm -rf $(OBJDIR)/
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rm -rf $(OBJDIR)/
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