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This directory contains three basic configurations for testing your UART
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This directory contains three basic configurations for testing your UART
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and proving that it works:
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and proving that it works:
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- helloworld: Displays the familiar "Hello, World!" message over and over. Tests the transmit UART port.
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- [helloworld](helloworld.v): Displays the familiar "Hello, World!" message over and over. Tests the transmit UART port.
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- linetest: Reads a line of text, then parrots it back. Tests both receive and transmit UART.
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- [echotest](echotest.v): Echoes any characters received directly back to the transmit port. Two versions of this exist: one that processes characters and regenerates them, and another that just connects the input port to the output port. These are good tests to be applied if you already know your transmit UART works. If the transmitter works, then this will help to verify that your receiver works. It's one fault is that it tends to support single character UART tests, hence the test below.
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- speechfifo: Recites the Gettysburg address over and over again. This can be used to test the transmit UART port, and particularly to test receivers to see if they can receive 1400+ characters at full speed without any problems.
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- [linetest](linetest.v): Reads a line of text, then parrots it back. Tests both receive and transmit UART.
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- [speechfifo](speechfifo.v): Recites the [Gettysburg address](../cpp/speech.txt) over and over again. This can be used to test the transmit UART port, and particularly to test receivers to see if they can receive 1400+ characters at full speed without any problems.
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Each of these configurations has a commented line defining OPT_STANDALONE within
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Each of these configurations has a commented line defining OPT_STANDALONE within
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it. If you uncomment this line, the configurations may be run as stand alone
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it. This option will automatically be defined if built within Verilator,
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configurations. (You will probably want to adjust the baud clock divider, to
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allowing the Verilator simulation to set the serial port parameters. Otherwise,
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be specific to the baud rate you wish to generate as well as the clock rate
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you should be able to run these files as direct top level design files. (You
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you will be generating this from.)
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will probably want to adjust the baud clock divider if so, so that you can set
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to the baud rate you wish to generate as well as the clock rate you will be
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generating this from.)
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If you leave OPT_STANDALONE commented, these demo programs should work quite
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nicely with a Verilator based simulation.
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