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https://opencores.org/ocsvn/wbuart32/wbuart32/trunk
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| Rev 13 |
Rev 15 |
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Line 51... |
//
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//
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`ifndef VERILATOR
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`ifndef VERILATOR
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`define OPT_STANDALONE
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`define OPT_STANDALONE
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`endif
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`endif
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//
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//
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//
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// Two versions of the UART can be found in the rtl directory: a full featured
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// UART, and a LITE UART that only handles 8N1 -- no break sending, break
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// detection, parity error detection, etc. If we set USE_LITE_UART here, those
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// simplified UART modules will be used.
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//
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// `define USE_LITE_UART
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//
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//
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module helloworld(i_clk,
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module helloworld(i_clk,
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`ifndef OPT_STANDALONE
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`ifndef OPT_STANDALONE
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i_setup,
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i_setup,
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`endif
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`endif
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o_uart_tx);
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o_uart_tx);
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tx_stb <= 1'b1;
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tx_stb <= 1'b1;
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else if ((tx_stb)&&(!tx_busy)&&(tx_index==4'hf))
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else if ((tx_stb)&&(!tx_busy)&&(tx_index==4'hf))
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tx_stb <= 1'b0;
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tx_stb <= 1'b0;
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// Bypass any hardware flow control
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// Bypass any hardware flow control
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wire rts;
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wire cts_n;
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assign rts = 1'b1;
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assign cts_n = 1'b0;
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`ifdef USE_LITE_UART
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txuartlite
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#(24'd868)
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transmitter(i_clk, tx_stb, tx_data, o_uart_tx, tx_busy);
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`else
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txuart transmitter(i_clk, pwr_reset, i_setup, tx_break,
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txuart transmitter(i_clk, pwr_reset, i_setup, tx_break,
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tx_stb, tx_data, rts, o_uart_tx, tx_busy);
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tx_stb, tx_data, cts_n, o_uart_tx, tx_busy);
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`endif
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endmodule
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endmodule
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