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https://opencores.org/ocsvn/wbuart32/wbuart32/trunk
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// Create a reset line that will always be true on a power on reset
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// Create a reset line that will always be true on a power on reset
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reg pwr_reset;
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reg pwr_reset;
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initial pwr_reset = 1'b1;
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initial pwr_reset = 1'b1;
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always @(posedge i_clk)
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always @(posedge i_clk)
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pwr_reset = 1'b0;
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pwr_reset <= 1'b0;
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// The UART Receiver
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// The UART Receiver
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//
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//
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// This is where everything begins, by reading data from the UART.
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// This is where everything begins, by reading data from the UART.
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//
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//
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// Data (rx_data) is present when rx_stb is true. Any parity or
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// Data (rx_data) is present when rx_stb is true. Any parity or
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// frame errors will also be valid at that time. Finally, we'll ignore
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// frame errors will also be valid at that time. Finally, we'll ignore
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// errors, and even the clocked uart input distributed from here.
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// errors, and even the clocked uart input distributed from here.
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wire rx_stb, rx_break, rx_perr, rx_ferr, rx_ignored;
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wire rx_stb, rx_break, rx_perr, rx_ferr;
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/* verilator lint_off UNUSED */
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wire rx_ignored;
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/* verilator lint_on UNUSED */
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wire [7:0] rx_data;
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wire [7:0] rx_data;
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`ifdef USE_LITE_UART
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`ifdef USE_LITE_UART
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rxuartlite #(24'd868)
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rxuartlite #(24'd868)
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receiver(i_clk, i_uart_rx, rx_stb, rx_data);
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receiver(i_clk, i_uart_rx, rx_stb, rx_data);
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