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% described.
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% described.
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%
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%
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To use the core, a couple of steps are required. First, wire it up. This
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To use the core, a couple of steps are required. First, wire it up. This
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includes wiring the {\tt i\_uart} and {\tt o\_uart} ports, as well as any
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includes wiring the {\tt i\_uart} and {\tt o\_uart} ports, as well as any
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{\tt i\_rts} and/or {\tt o\_cts} hardware flow control. The
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{\tt i\_cts\_n} and/or {\tt o\_rts\_n} hardware flow control. The
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{\tt rxuart.v} and {\tt txuart.v} files may be wired up for use individually,
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{\tt rxuart.v} and {\tt txuart.v} files may be wired up for use individually,
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or as part of a large module such as the example in{\tt wbuart-insert.v}.
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or as part of a large module such as the example in{\tt wbuart-insert.v}.
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Alternatively, the {\tt wbuart.v} file may be connected to a straight 32--bit
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Alternatively, the {\tt wbuart.v} file may be connected to a straight 32--bit
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wishbone bus.
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wishbone bus.
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Second, set the UART configuration register. This is ideally set by setting
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Second, set the UART configuration register. This is ideally set by setting
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| Line 597... |
Line 597... |
{\tt if (!clk)} \= \\
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{\tt if (!clk)} \= \\
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\> {\tt tb->i\_uart\_rx} {\tt = } {\tt uartsim(tb->o\_uart\_tx);}
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\> {\tt tb->i\_uart\_rx} {\tt = } {\tt uartsim(tb->o\_uart\_tx);}
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\end{tabbing}
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\end{tabbing}
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For those interested in hardware flow control, the core also offers an
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For those interested in hardware flow control, the core also offers an
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{\tt i\_rts} input to control the flow out of our transmitter, and an
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{\tt i\_cts\_n} input to control the flow out of our transmitter, and an
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{\tt o\_cts} output when the receiver is full.
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{\tt o\_rts\_n} output to indicate when the receiver is full. Both of these
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wires are active low.
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For those not interested in flow control there are three
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possibilities. First, one can set the module parameter
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{\tt HARDWARE\_FLOW\_CONTROL\_PRESENT} to zero which will disable hardware
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flow control. This will also permanently set the hardware flow control is off
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bit in the setup register. Second, hardware flow control can be disabled by
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connecting a {\tt 1'b0} wire to {\tt i\_cts\_n} and by ignoring the
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{\tt o\_rts\_n} output. In this case, the hardware flow control setup bit
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becomes an unused flip flop within the driver. The third way to disable
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hardware flow control is to simply disable it within the setup register. In
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general, these approaches will only affect the transmitter's operation and how
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the {\tt o\_rts\_n} bit gets set.
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A more detailed discussion of the connections associated with these modules
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A more detailed discussion of the connections associated with these modules
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can begin with Tbl.~\ref{tbl:rxports},
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can begin with Tbl.~\ref{tbl:rxports},
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\begin{table}\begin{center}\begin{portlist}
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\begin{table}\begin{center}\begin{portlist}
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{\tt i\_clk} & 1 & Input & The system clock \\\hline
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{\tt i\_clk} & 1 & Input & The system clock \\\hline
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| Line 626... |
Line 639... |
{\tt i\_setup} & 31 & Input & The 31--bit setup register \\\hline
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{\tt i\_setup} & 31 & Input & The 31--bit setup register \\\hline
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{\tt i\_break} & 1 & Input & Set to true to place the transmit channel into a break condition\\\hline
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{\tt i\_break} & 1 & Input & Set to true to place the transmit channel into a break condition\\\hline
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{\tt i\_wr} & 1 & Input & An input strobe. Set to one when you wish to transmit data, clear once it has been accepted\\\hline
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{\tt i\_wr} & 1 & Input & An input strobe. Set to one when you wish to transmit data, clear once it has been accepted\\\hline
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{\tt i\_data} & 8 & Input & The data to be transmitted, ignored unless
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{\tt i\_data} & 8 & Input & The data to be transmitted, ignored unless
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{\tt (i\_wr)\&\&(!o\_busy)} \\\hline
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{\tt (i\_wr)\&\&(!o\_busy)} \\\hline
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{\tt i\_rts} & 1 & Input & A hardware flow control wire, true if the receiver is ready to receive\\\hline
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{\tt i\_cts\_n} & 1 & Input & A hardware flow control wire, true if the transmitter is cleared to send, active low\\\hline
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{\tt o\_uart} & 1 & Output & The wire to be connected to the external port\\\hline
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{\tt o\_uart} & 1 & Output & The wire to be connected to the external port\\\hline
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{\tt o\_busy} & 1 & Output & True if the transmitter is busy, false if it will receive data\\\hline
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{\tt o\_busy} & 1 & Output & True if the transmitter is busy, false if it will receive data\\\hline
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\end{portlist}\caption{TXUART port list}\label{tbl:txports}
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\end{portlist}\caption{TXUART port list}\label{tbl:txports}
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\end{center}\end{table}
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\end{center}\end{table}
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detailing the I/O ports of the UART transmitter, and Tbl.~\ref{tbl:wbports}
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detailing the I/O ports of the UART transmitter, and Tbl.~\ref{tbl:wbports}
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\begin{table}\begin{center}\begin{tabular}{|p{1.15in}|p{0.1in}|p{0.75in}|p{3.375in}|}
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\begin{table}\begin{center}\begin{tabular}{|p{1.15in}|p{0.1in}|p{0.75in}|p{3.375in}|}
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\rowcolor[gray]{0.85} Port & W & Direction & Description \\\hline\hline
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\rowcolor[gray]{0.85} Port & W & Direction & Description \\\hline\hline
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{\tt i\_uart\_rx}& 1 & Input & The receive wire coming from the external port\\\hline
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{\tt i\_uart\_rx}& 1 & Input & The receive wire coming from the external port\\\hline
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{\tt o\_uart\_tx}& 1 & Output & The transmit wire to be connected to the external port\\\hline
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{\tt o\_uart\_tx}& 1 & Output & The transmit wire to be connected to the external port\\\hline
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{\tt i\_rts}& 1 & Input & The hardware flow control {\tt ready-to-send} (i.e. receive) input for the transmitter\\\hline
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{\tt i\_cts\_n}& 1 & Input & The hardware flow control {\tt clear-to-send} input for the transmitter, active low\\\hline
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{\tt o\_cts}& 1 & Output & The hardware flow control {\tt clear-to-send} output\\\hline
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{\tt o\_rts\_n}& 1 & Output & The hardware flow control {\tt ready-to-send} (receive) output, also active low\\\hline
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{\tt o\_uart\_rx\_int} & 1 & Output & True if a byte may be read from the receiver\\\hline
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{\tt o\_uart\_rx\_int} & 1 & Output & True if a byte may be read from the receiver\\\hline
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{\tt o\_uart\_tx\_int} & 1 & Output & True if a byte may be sent to the transmitter\\\hline
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{\tt o\_uart\_tx\_int} & 1 & Output & True if a byte may be sent to the transmitter\\\hline
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{\tt o\_uart\_rxfifo\_int}&1& Output & True if the receive FIFO is half full\\\hline
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{\tt o\_uart\_rxfifo\_int}&1& Output & True if the receive FIFO is half full\\\hline
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{\tt o\_uart\_txfifo\_int}&1& Output & True if the transmit FIFO is half empty\\\hline
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{\tt o\_uart\_txfifo\_int}&1& Output & True if the transmit FIFO is half empty\\\hline
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\end{tabular}\caption{WBUART port list}\label{tbl:wbports}
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\end{tabular}\caption{WBUART port list}\label{tbl:wbports}
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